Job
Description: SoC Implementation & Tapeout Engineer
Company: Ananant Systems
Location: Noida / Bengaluru
Department: Silicon Engineering — SoC
Implementation
Experience: 5–15 years
Education: B.Tech / M.Tech / PhD —
Electronics, Computer Engineering, or Electrical Engineering
About
the Role
Ananant
Systems is developing a proprietary AI-native DSP SoC targeting 5G/6G wireless,
Edge AI inference, Vision AI, camera, video, and radar applications. We are
looking for an experienced SoC Implementation & Tapeout Engineer to own
end-to-end SoC integration, synthesis, timing & power sign-off, DFT, and
tapeout execution — from RTL handoff to GDSII delivery and post-silicon
support. The role reports directly to the Chief Architect / CTO.
Key
Responsibilities
Integrate
DSP datapath IPs, processor subsystems, memory controllers, and high-speed
peripherals (PCIe Gen3/4, USB3, JESD204B, MIPI CSI-2/DSI, DDR/LPDDR, etc.) into
the top-level SoC.
Define
and implement clock, reset, and power architectures (UPF) across multiple
voltage domains.
Drive
hierarchical synthesis, STA timing closure (PrimeTime), lint/CDC checks, and
formal equivalence across all design stages.
Perform
dynamic & static power analysis and optimization to meet power budgets.
Own
DFT implementation: scan chain stitching, MBIST/LBIST, JTAG TAP, and boundary
scan.
Manage
complete tapeout flow — sign-off checklist, ECOs, documentation, and foundry
handoff.
Support
post-silicon bring-up, scan test debug, and silicon characterization.
Requirements
Required
Skills & Competencies
Expert
level: Synthesis (DC/Genus), STA (PrimeTime), Lint & CDC (Spyglass), Power
(UPF/Joules), Tapeout execution & sign-off.
Advanced
level: DFT architecture, Formal Equivalence (Formality/Conformal), Clock/Reset
design, Peripheral IP integration (PCIe, JESD204B, MIPI, DDR).
Strong
understanding of FinFET nodes and multi-domain SoC integration.
Mandatory
Experience
Named
contributor on at least 2 commercial tapeouts at 22nm or below.
Direct
ownership of sign-off (synthesis/timing/power/DFT) for at least one IP block or
SoC subsystem through GDS handoff.
Experience
in post-silicon debug or bring-up support.
Strong
Advantage
Tapeout
experience on heterogeneous SoCs with DSP + AI + Multimedia accelerators.
Hands-on
work with high-speed SerDes (PCIe, JESD204B) and DDR/LPDDR controllers.
Prior
FinFET tapeouts (16nm/12nm/7nm).
Benefits
What
We Offer
Full
ownership of implementation and tapeout of a next-generation AI-native DSP SoC.
Direct
collaboration with a Chief Architect having 20+ years of 4G/5G modem silicon
experience.
Access
to advanced FinFET technology through foundry partnerships.
Competitive
CTC + meaningful ESOPs in an early-stage semiconductor startup.
To
Apply: Send your CV, a list of tapeouts you have contributed to (with your specific
sign-off responsibilities), and any publications/patents to: [email protected]
Skills Required
- 5-15 years of experience in SoC implementation and tapeout
- B.Tech, M.Tech, or PhD in Electronics, Computer Engineering, or Electrical Engineering
- Expert-level experience with synthesis using Design Compiler or Genus
- Expert-level experience with static timing analysis using PrimeTime
- Expert-level experience with lint and CDC analysis using SpyGlass
- Expert-level experience with power analysis using UPF and Joules
- Expert-level experience in tapeout execution and sign-off
- Advanced experience with DFT architecture
- Advanced experience with formal equivalence using Formality or Conformal
- Advanced experience with clock and reset design
- Advanced experience integrating PCIe, JESD204B, MIPI, DDR, and related peripheral IP
- Strong understanding of FinFET nodes and multi-domain SoC integration
- Named contributor on at least two commercial tapeouts at 22nm or below
- Direct ownership of synthesis, timing, power, or DFT sign-off for at least one IP block or SoC subsystem through GDS handoff
- Experience supporting post-silicon debug or bring-up
- Tapeout experience with heterogeneous SoCs containing DSP, AI, or multimedia accelerators
- Hands-on experience with high-speed SerDes, PCIe, JESD204B, and DDR/LPDDR controllers
- Prior FinFET tapeout experience at 16nm, 12nm, or 7nm
What We Do
Ananant Systems is an India-based semiconductor and wireless systems company developing advanced connectivity, computing, and security solutions for 5G and 6G infrastructure and devices. Its offerings include proprietary intellectual property, chip design, semiconductor products, software, and systems developed in India. The company focuses on wireless technologies, including secure communications and software-upgradeable processing for infrastructure, combining semiconductor engineering with systems innovation for global markets and next-generation wireless applications.
