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Reposted 10 Hours AgoSaved
In-Office
Sunnyvale, CA, USA
175K-250K Annually
Senior level
175K-250K Annually
Senior level
Hardware • Semiconductor • Manufacturing
The CPU Compiler Lead will optimize code for a high-performance RISC-V CPU, manage integration of language standards, and lead compiler optimization efforts.
Top Skills: Aarch64Assembly LanguageAvxC/C++GccLlvmRisc-VSveX86-64
Reposted 10 Hours AgoSaved
In-Office
Sunnyvale, CA, USA
175K-250K Annually
Senior level
175K-250K Annually
Senior level
Hardware • Semiconductor • Manufacturing
Lead the development of a high-performance compiler stack for GPU architecture, focusing on optimization passes, collaboration with hardware architects, and team coordination.
Top Skills: C++CudaDirectxGccLlvmMetalOpenclOpenglVulkan
Reposted 4 Days AgoSaved
In-Office
Sunnyvale, CA, USA
160K-220K Annually
Senior level
160K-220K Annually
Senior level
Hardware • Semiconductor • Manufacturing
The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.
Top Skills: Cadence XceliumPythonSynopsys Design CompilerSynopsys VcsSystemverilogTclVerilog
Reposted 4 Days AgoSaved
In-Office
Sunnyvale, CA, USA
250K-280K Annually
Senior level
250K-280K Annually
Senior level
Hardware • Semiconductor • Manufacturing
As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.
Top Skills: Cadence XceliumPythonSynopsys VcsSynopsys VerdiSystemverilogTclUvm
Reposted 4 Days AgoSaved
In-Office
Sunnyvale, CA, USA
200K-220K Annually
Senior level
200K-220K Annually
Senior level
Hardware • Semiconductor • Manufacturing
Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.
Top Skills: Cadence InnovusMentor CalibrePythonSynopsys Icc2Synopsys PrimetimeTcl
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6 Days AgoSaved
In-Office or Remote
Sunnyvale, CA, USA
75K-120K Annually
Senior level
75K-120K Annually
Senior level
Hardware • Semiconductor • Manufacturing
Coordinate customer and partner onboarding, manage executive support and calendars, track sales pipeline and KPIs, maintain BD documentation, coordinate cross-functional projects, organize travel, support recruiting, and build scalable onboarding and enablement processes to grow business development operations.
Top Skills: ConfluenceCRMHubspotMicrosoft PowerpointMicrosoft TeamsOutlookSalesforceSharepoint
Reposted 6 Days AgoSaved
In-Office
Sunnyvale, CA, USA
200K-250K Annually
Senior level
200K-250K Annually
Senior level
Hardware • Semiconductor • Manufacturing
Lead end-to-end hardware architecture for next-generation GPU compute platforms, define high-speed PCB topologies and PDNs, optimize PCIe/serdes fabrics, coordinate SI/PI and thermal co-design, and lead technical engagement with JDM/ODM partners through bring-up, failure analysis, and HVM transition.
Top Skills: 112G Pam4224G Pam4BertBmcCadence AllegroCxlI2CInfinity FabricLiquid CoolingNvlinkOpen Compute ProjectOrcadOscilloscopesPcie Gen5Pcie Gen6PdnSi/PiSmbusSpiUa LinkVna
Reposted 6 Days AgoSaved
In-Office
Sunnyvale, CA, USA
145K-175K Annually
Senior level
145K-175K Annually
Senior level
Hardware • Semiconductor • Manufacturing
The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.
Top Skills: AWSBashDockerGrafanaKubernetesLinuxAzureOpenshiftPrometheusProxmoxPythonVmware Vsphere
Reposted 7 Days AgoSaved
In-Office or Remote
Sunnyvale, CA, USA
85K-95K Annually
Junior
85K-95K Annually
Junior
Hardware • Semiconductor • Manufacturing
Coordinate social media content and engagement, manage posting schedules, analyze performance, and support influencer marketing initiatives at Bolt Graphics.
Top Skills: Google SuiteMS Office
Reposted 8 Days AgoSaved
In-Office
Sunnyvale, CA, USA
150K-220K Annually
Expert/Leader
150K-220K Annually
Expert/Leader
Hardware • Semiconductor • Manufacturing
The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.
Top Skills: CPythonSynopsys Tools
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