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Manages graphics engineering programs, schedules, deliverables, global team coordination, risk mitigation, stakeholder reporting, and project-management process improvements. Serves as the primary internal contact for graphics software development programs while balancing product goals, delivery speed, and competing priorities. Requires close collaboration with engineers, executives, and technical and non-technical teams. The role is onsite in the Bay Area three to four days weekly with occasional travel.

Serve as the technical counterpart to the commercial team for HPC and computational engineering customers. Lead workload discovery, performance analysis, benchmarking, proofs of concept, technical evaluations, and deployment planning. Translate customer needs into engineering requirements, explain Bolt’s GPU architecture, resolve technical blockers, develop technical materials, and assess technical fit. Support strategic partners, national laboratories, government organizations, and industry events while bringing customer feedback into product strategy.

Own end-to-end hardware system architecture for graphics compute platforms, GPU servers, and PCIe graphics form factors. Define physical topologies, high-speed interconnects, PCB stack-ups, power delivery, telemetry, and management infrastructure. Lead JDM/ODM engineering partners through layout, bring-up, validation, debug, failure analysis, DFX reviews, and high-volume manufacturing. Collaborate across silicon, signal and power integrity, thermal, and mechanical engineering teams to deliver high-performance graphics hardware.

The RTL Design / Microarchitecture Engineer will define and implement microarchitectural components, optimize performance, and collaborate with cross-functional teams.

As a Principal Design Verification Engineer, you will lead verification strategies and teams for complex IPs or full-chip SoCs, ensuring high-quality silicon delivery through comprehensive verification methodologies and cross-functional collaboration.

Responsible for full-chip or block-level physical design from netlist to GDSII, ensuring timing, power, and area targets are met. Collaborates with teams for design convergence and performs DRC/LVS/EM/IR debugging.

The Site Reliability Engineer will design, implement, and manage reliable infrastructure and services, ensuring operational excellence and uptime.

The Senior Design Verification Engineer develops and verifies silicon IP, optimizing and characterizing performance using advanced tools, while leading a team.

Lead end-to-end ASIC physical implementation from netlist to GDSII, covering synthesis support, floorplanning, placement, CTS, routing, signoff, timing closure across corners, ECO flows, physical verification (DRC/LVS/EM/IR), integrating hard macros, and automating PD flows with TCL/Python while collaborating with RTL, verification, and foundry teams to meet PPA targets.

Design and implement RTL and microarchitectural components for high-performance SoC/IP. Develop SystemVerilog/Verilog modules, optimize PPA, collaborate with verification and physical design teams, support IP integration and silicon bring-up, and contribute to documentation and methodology improvements.