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Lead IC layout engineer responsible for autonomous end-to-end layout and physical verification from cell to full-chip, enforcing DRM rules, running sign-off flows, authoring waivers, improving BKMs and workflows, leading cross-functional projects, mentoring engineers, and ensuring flawless tape-out delivery.

Lead autonomous IC layout and physical verification across hierarchies (unit cells to full-chip). Own DRC/LVS sign-off, maintain DRM compliance for multiple process nodes, drive workflow and BKM improvements, lead teams, mentor engineers, manage client relationships, and run post-mortems to ensure timely, high-quality silicon delivery.

Lead design, implementation, and testing of embedded firmware. Create specifications, verification plans, and regression tests. Debug, maintain test environments, mentor junior engineers, and collaborate with hardware and software teams to ensure firmware quality and customer support.

The Senior Analog Layout Engineer leads layout design and optimization of analog circuits, ensuring performance through advanced techniques and mentoring junior engineers.

Lead design, analysis, and verification of analog, digital, and mixed-signal circuits (Logic/IO/PHY/Memory/PMIC/Converters). Develop library and custom cells, create testbenches, drive R&D and process improvements, manage projects and resources, mentor junior engineers, ensure quality, and collaborate cross-functionally to resolve issues and meet client requirements.

The IC Layout Engineer develops full-custom layouts for analog and mixed-signal blocks, supports floor-planning and verification, and collaborates with design teams.

Lead and execute digital physical design from netlist to GDS, including floorplanning, power planning, placement, CTS, routing, timing closure, verification support, ECOs, and tapeout readiness while coordinating cross-functional teams and tracking project risks and deliverables.