Staff Digital Implementation Engineer

The Staff Physical Design / PnR Implementation Engineer is responsible for the execution and technical leadership of digital implementation projects, with focus on place-and-route, timing closure, physical verification, and tapeout readiness.

The role requires strong hands-on implementation capability while also leading assigned project activities, coordinating tasks, tracking progress, and serving as the technical owner for physical design execution. The position is expected to contribute directly as an individual contributor while ensuring that project deliverables are completed with quality, schedule visibility, and proper closure.

• Perform hands-on digital implementation from netlist to GDS.
• Execute floorplanning, power planning, placement, clock tree synthesis, routing, optimization, and design closure.
• Implement block-level or top-level physical design based on project requirements, technology rules, and design constraints.
• Work on timing, congestion, power, area, signal integrity, and routability optimization.
• Support ECO implementation, including functional ECOs, timing ECOs, and routing ECOs.
• Prepare physical design databases and deliverables for integration, review, and tapeout.

• Perform static timing analysis support and timing closure across applicable corners and modes.
• Debug and resolve setup, hold, transition, capacitance, clock skew, congestion, and routing-related issues.
• Work with design, verification, DFT, CAD/EDA, and signoff teams to resolve implementation and closure issues.
• Support closure for power integrity, IR drop, EM, signal integrity, crosstalk, and physical verification requirements as applicable.
• Ensure implementation meets project targets for timing, power, area, reliability, and manufacturability.

• Support DRC, LVS, antenna, density, ERC, and related physical verification checks.
• Coordinate with CAD/EDA and signoff teams to resolve rule violations and tool-related issues.
• Ensure implementation outputs are clean, complete, and aligned with tapeout requirements.
• Maintain proper version control, run directories, reports, logs, scripts, and documentation.

• Lead physical design implementation activities for assigned projects or blocks.
• Define and coordinate implementation tasks based on project priorities, complexity, schedule, and team capability.
• Track progress, dependencies, risks, blockers, and deliverables.
• Provide clear technical updates on implementation status, closure progress, issues, and schedule impact.
• Identify and escalate technical or schedule risks in a timely manner.
• Review implementation results and ensure quality of outputs before handoff or signoff.
• Guide engineers on implementation flow, debugging, closure strategies, and best practices.

• Work closely with RTL design, DFT, verification, CAD/EDA, timing, and signoff teams.
• Clarify design constraints, floorplan requirements, timing expectations, and implementation assumptions.
• Coordinate handoffs and feedback between front-end design and back-end implementation teams.
• Support project reviews, technical discussions, closure planning, and tapeout preparation.

• Bachelor’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 7 years of experience in digital physical design, implementation, or place-and-route.
• Strong hands-on experience with digital implementation from synthesis or netlist handoff through GDS delivery.
• Experience leading or coordinating physical design activities within a project team.
• Strong understanding of digital implementation fundamentals, including:
  • Floorplanning
  • Power planning
  • Placement optimization
  • Clock tree synthesis
  • Routing and routing optimization
  • Timing closure
  • Signal integrity and crosstalk awareness
  • IR drop and EM considerations
  • Physical verification and tapeout readiness
• Experience with timing analysis and multi-mode, multi-corner closure.
• Experience debugging implementation issues related to timing, congestion, routing, constraints, and physical verification.
• Ability to interface effectively with RTL, DFT, verification, CAD/EDA, timing, signoff, and project stakeholders.
• Strong ownership, accountability, problem-solving ability, and delivery discipline.
• Ability to lead project execution while remaining hands-on as an individual contributor.

• Prior experience as a Physical Design Lead, PnR Lead, Implementation Lead, or project technical owner.
• Experience with block-level and/or top-level implementation.
• Experience in advanced-node or FinFET technologies.
• Experience supporting full-chip integration and tapeout activities.
• Experience with low-power implementation methodologies such as UPF/CPF.
• Experience with DFT-aware implementation and scan-related physical design considerations.
• Experience using Cadence Innovus and related implementation tools.
• Familiarity with scripting and flow automation using Tcl, Python, Perl, Shell, or similar languages.
• Experience with signoff tools and methodologies for STA, DRC, LVS, IR/EM, and signal integrity.

• Digital physical design implementation
• Place-and-route execution
• Timing closure
• Physical verification and signoff support
• Floorplanning and power planning
• Clock tree synthesis
• Routing optimization
• ECO implementation
• Project execution leadership
• Task coordination and progress tracking
• Cross-functional communication
• Risk identification and escalation
• Delivery ownership

The Staff Physical Design / PnR Implementation Engineer is expected to deliver high-quality digital implementation results while leading assigned project execution. The role requires strong hands-on PnR capability, timing and closure expertise, and the ability to coordinate tasks, track risks, guide engineers, and ensure that physical design deliverables are completed according to project requirements and tapeout readiness standards.