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Develop and verify high-speed SerDes mixed-signal IP across digital, analog, DSP, and firmware-hardware systems. Responsibilities include constrained-random and coverage-driven verification, advanced verification environment development, DSP datapath validation, and root-cause analysis. The role involves the full verification lifecycle from specification through tape-out sign-off and uses AI-assisted engineering tools. Candidates should have a relevant bachelor’s degree and 0–3 years of hardware design or verification experience.

Develop and validate semiconductor products from concept through mass production. Responsibilities include defining product requirements, performing silicon validation and characterization, developing test hardware and software, analyzing yield and failures, debugging issues, documenting results, and improving development processes in collaboration with design, validation, and manufacturing teams.

Supports APAC corporate income, GST/VAT, withholding tax, transfer pricing, tax provision, reporting, filings, audits, and advisory activities. Coordinates statutory deadlines, documentation, reconciliations, and external advisors while partnering with Finance, Legal, HR, Payroll, Procurement, and IT. Improves tax processes, automation, controls, ERP data integrity, and documentation retention. Provides practical guidance on tax requirements, remote-work and permanent-establishment impacts, incentives, and tax-sensitive business initiatives across Malaysia, India, and other APAC jurisdictions.

Architects FPGA IP for O-RAN, eCPRI, and CPRI applications in 5G networks. Leads customer and partner technical discussions while managing FPGA IP software, validation, and architecture teams. Oversees design, RTL development, simulation, hardware validation, troubleshooting, and debugging. Sets goals, coaches employees, manages performance, and ensures teams deliver results. Requires expertise in FPGA development, wireless standards, timing closure, clock-domain crossing, reset architecture, and standard interfaces.

Designs and verifies synthesizable RTL and DSP algorithms for mixed-signal IP, including SerDes, ADC/DAC, calibration, equalization, and clock/data recovery systems. Responsibilities include microarchitecture, synthesis, timing closure, low-power design, AMS co-simulation, silicon bring-up, laboratory debugging, documentation, code reviews, and mentoring junior engineers. Collaborates closely with analog teams on digital-analog interfaces and adaptive control flows.

Lead end-to-end FPGA development kit execution across board architecture, RTL, firmware, validation, manufacturing, and supply chain. Coordinate global engineering teams, design partners, ODMs, contract manufacturers, and suppliers. Drive BOM planning, cost optimization, component availability, obsolescence management, technical risk resolution, manufacturing execution, and platform robustness improvements.

Manage and grow strategic OEM customer accounts, develop sales strategies, exceed revenue targets, provide tailored semiconductor solutions, and serve as the primary account contact. Collaborate with business solutions, product marketing, and engineering teams; monitor markets and competitors; and deliver forecasting, reporting, and analysis to senior leadership. The role focuses on complex technical sales cycles and long-term customer relationships in the Los Angeles area.

Designs and develops analog circuits for advanced semiconductor process nodes and mixed-signal IPs. Responsibilities include circuit simulation, verification, floorplan optimization, layout review, test-plan development, and optimizing designs for power, performance, area, timing, and yield. The engineer collaborates with architecture, layout, and verification teams, tracks design issues, reports progress, and drives technical resolutions.

Develops FPGA applications for 5G core, RAN, and edge solutions, focusing on virtualization, performance optimization, security, and DSP algorithms. Handles customer escalations, supports field teams and distributors, contributes to development projects and reference designs, creates training materials, and collaborates with global R&D, application, and customer teams. Requires expertise in 5G architecture, DSP, FPGA and ASIC design flows, RTL-based design, transceiver methodologies, and complex system-level problem solving.

Design and develop analog circuits for advanced semiconductor process nodes and mixed-signal IP. Create floorplans, review layouts, develop test plans, verify circuit functionality, and optimize designs for power, performance, area, timing, and yield. Collaborate with architecture, layout, and verification teams, track design issues, report progress, and drive technical resolutions.