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Join a graduate program developing high-speed FPGA protocol IP: perform RTL coding, verification, simulation, emulation prototyping, and hardware validation while using EDA tools and scripting to integrate and test FPGA-based systems.

Develop and execute DFT and test-logic verification plans for FPGA SoC/IP. Build and maintain SystemVerilog/UVM testbenches, run functional/regression and coverage-driven verification, debug RTL/testbench failures, collaborate with architects and design teams, and track verification metrics.

Define and drive end-to-end semiconductor package architecture meeting electrical, mechanical, thermal, cost, and reliability targets. Lead package design decisions, troubleshoot materials/process issues, collaborate with silicon, hardware, and manufacturing teams, and improve packaging processes and quality for production readiness.

Develop and execute verification plans and reusable SystemVerilog/UVM testbenches for FPGA IP, subsystems, and SoC designs. Create constrained-random and directed tests, SVA assertions, and coverage models; debug failures via simulation/emulation; collaborate with RTL, firmware, and validation teams to achieve verification closure and support post-silicon bring-up.

Design and develop end-to-end platform hardware and PCBs from requirements to tape-out. Perform circuit design, simulation, component selection, BOM trade-offs, layout rules, and platform bring-up. Collaborate with architects, verification, manufacturing, and technicians for power-on, debugging, validation, and customer delivery.

Lead architecture, microarchitecture, RTL design, and technical direction for scalable Network-on-Chip IPs for FPGA platforms. Develop RTL, prototypes, simulation models, and software bring-up; optimize for power, performance, area, and reliability. Guide verification, collaborate with cross-functional teams, mentor engineers, and apply EDA and AI-enabled automation to meet project schedules and quality goals.

Lead thermal and thermomechanical characterization and qualification of advanced 2.5D/3D semiconductor packages. Develop and calibrate FEA models, define and run warpage/coplanarity/reliability tests, perform lifetime prediction and failure analysis, own DFMEA activities, and produce customer reports on package reliability.

Join the Quartus Device Modeling organization to tackle software and hardware challenges in FPGA development, focusing on data abstraction, complex algorithms, and AI/ML integration.

Lead end-to-end SI/PI design and verification for high-speed interconnects across silicon, package, and board. Define simulation methodologies, run DOE, establish SI/PI design rules, review layouts, perform post-layout simulations, and collaborate with silicon, package, and board teams to optimize SERDES, memory interfaces, FPGA fabric, and PDNs using advanced EDA tools and AI-assisted techniques.

Responsible for timing closure and signoff of FPGA/SoC and subsystem timing via static timing analysis. Derive and provide interface timing constraints, perform final timing signoff, and collaborate with design, architecture, and physical design teams for timing convergence and closure.