Logic Designer

Altera is seeking a highly motivated and skilled Logic Designer to contribute to the development of cutting-edge programmable logic devices. This role involves designing, verifying, and implementing complex digital logic for our next-generation FPGA products.

Job Title: Senior Logic/DSP Design Engineer – Mixed Signal

Location: Israel

Department: Analog Mixed Signal Serdes (AMS)

About the Role
We are seeking a Senior Logic/DSP Design Engineer to develop digital logic and DSP algorithms supporting mixed-signal IP blocks (e.g., high-speed SerDes, ADC/DAC digital, calibration engines, and control logic). This role bridges the digital and analog domains — translating system-level and DSP algorithms into synthesizable RTL, and working closely with analog/mixed-signal architects to close the loop on calibration, equalization, and adaptive control.

Key Responsibilities

• Micro-Architect Design and implement digital logic (RTL) for mixed-signal subsystems — calibration state machines, digital filters, adaptive equalization, clock/data recovery digital loops, etc.

• Collaborate with analog design teams to define digital-analog interfaces, calibration flows, and control logic.

• Perform RTL-to-gate synthesis, timing closure, and low-power design techniques for mixed-signal digital blocks.

• Build and maintain block level verification environments (Verilog) for digital logic tied to analog behavior (mixed-signal verification, AMS co-simulation).

• Support silicon bring-up and debug — correlating digital logic behavior with analog measurements in the lab.

• Document architecture, algorithms, and design decisions; participate in design and code reviews.

• Mentor junior engineers on digital design practices within a mixed-signal flow.

• BSC/MSC in Electrical Engineering.

• 7+ years of experience in digital logic design, with exposure to mixed-signal or DSP projects.

• Strong RTL design skills (Verilog) and synthesis flow experience

• Solid understanding of DSP fundamentals (filtering, sampling, quantization, timing recovery).

• Familiarity with mixed-signal verification methodologies (AMS simulation, Verilog-AMS, real number modeling).

Preferred Qualifications

• Experience with high-speed SerDes, PCIe, DisplayPort, Ethernet or similar interface standards.

• Exposure to calibration/adaptation algorithms for ADCs, DACs, or equalizers.

• Familiarity with low-power design techniques and static timing analysis (STA).

• Experience working directly with analog designers on digital-analog co-design.