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Manage the Sustaining group, providing technical guidance and driving HW, Product, and System Qualification buy-off for mass production while leading test improvements and ensuring minimal testing issues.

As an Electronics Engineer II at SiTime, you will provide technical support to customers, analyze applications, debug systems, and contribute to infrastructure projects while mentoring lower-ranked engineers.

The NPI Product Engineer will manage product transfers to operations, handle data analysis, maintain test lab efficiency, and collaborate with teams to define test flows and assist with equipment setup.

The Senior Test Development Engineer develops hardware and software test solutions for precision timing devices, ensuring quality and efficiency from product development to production launch.

The Sr. Analog Mixed-Signal Design Engineer designs precision timing circuits using MEMS technology, collaborates on design validation, and participates in chip evaluations.

Lead SiTime's packaging technology and roadmap for MEMS devices, collaborating with OSATs and IC teams to enable performance, reliability, manufacturability, and cost targets. Oversee mechanical and electrical package design, advanced material selection and characterization, lab workflows, yield and supply scaling, KPI-driven process productivity, and build high-performance global teams to execute NPI through volume production.

Lead strategy, design, implementation, and support of B2B and middleware integrations. Manage full lifecycle projects, liaise with external partners, ensure security/compliance, mentor team members, establish integration standards, troubleshoot complex issues, and support scalable, maintainable connectivity across internal systems and external customers and suppliers.

Lead Oracle Fusion Cloud ERP architecture across Finance, Supply Chain, Manufacturing and O2C. Design integrations using OIC, APIs, EDI and file interfaces; define reference architectures, security, data migration and compliance (SOX/ITGC). Drive roadmaps, chair architecture reviews, mentor teams, oversee implementations, troubleshoot production issues, and liaise with stakeholders and Oracle Support in a high-growth fabless semiconductor environment.

Lead chip top-level planning and perform block- and cell-level custom layouts for CMOS/BiCMOS. Drive floorplanning, power distribution, shielding, verification (DRC/LVS/ERC), chip integration and tape-out. Mentor junior and offshore layout engineers and help establish cross-site layout methodologies and processes.

Lead verification efforts for MEMS timing ICs by developing SystemVerilog/UVM environments, SV-RNM analog models, SVAs, coverages, running and debugging simulations, and reviewing results for tape-out. Collaborate with analog, digital, and test teams and drive verification plans from specs to sign-off.