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The role involves leading technology ramp-up and process transfers for logic/RF devices, collaborating with foundries, and ensuring manufacturability and performance targets are met.

The role involves implementing compiler modules, developing production-grade components, performing optimizations, and mentoring junior engineers in a collaborative environment focused on edge AI solutions.

Lead cross-functional execution of Automotive ASIL-B/D and data center SoCs from definition through post-silicon productization. Drive architecture decisions, coordinate IP/technology/packaging partners, resolve handoffs across frontend, verification, AMS, DFT, emulation, physical implementation, and validation, create project plans, mentor engineers, and ensure high quality, reliability, and timely delivery under resource and schedule constraints.

Lead design and implementation of the AI/ML compiler front-end and model conversion pipelines. Build Python-based converters for ONNX, TensorFlow, and PyTorch, implement graph construction, IR lowering, and graph optimization passes, and drive validation, testing, and CI/CD. Provide technical leadership and mentor engineers while collaborating with backend, runtime, performance, and hardware teams.

Responsible for translating customer requirements into product specifications, designing secure JavaCard applets, ensuring testing procedures, and guiding development teams.

Design and verify digital SoC sub-circuits: RTL coding, synthesis, STA, formal verification, power analysis, DFT and post-silicon debug. Collaborate with analog and software teams, produce design documentation, and follow team design methodologies to meet quality and schedule targets.

Own SoC program execution from definition through tape-out and post-silicon support. Provide technical leadership across architecture, RTL, DFT, verification, implementation, validation and system teams. Lead cross-functional coordination, manage schedule, resources, risks, and stakeholder communications, and ensure tape-out and silicon readiness with post-silicon validation and issue resolution.

Lead expansion of NXP's China Edge AI and Physical AI ecosystem by building and enabling partnerships with universities, developers, system integrators, and solution providers. Drive developer engagement, coordinate cross-functional technical resources for demos and POCs, create enablement assets, and align ecosystem activity with business and market priorities.

Lead OSAT-wide external package innovation initiatives and governance from concept to production. Define templates, success criteria, and BKMs; maintain technology roadmaps; support NPI/NTI execution at external OSATs; ensure compliance, SME alignment, assembly readiness, and safe production launches while resolving technical and project issues across sites.

Define, design, verify and evaluate digital functions for mixed-signal IPs, subsystems or ICs per specifications. Ensure quality and reliability, participate in digital and system-level problem solving, and author design-specific documentation.