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The role involves precision sample preparation for semiconductor packaging and die inspection, utilizing a variety of imaging and processing techniques. Responsibilities include operating advanced equipment, documenting results, and contributing to new methodologies in FA techniques.

Design and develop reusable IP blocks for SoC integration: create micro-architecture, implement RTL (Verilog/SystemVerilog/VHDL), optimize for PPA, run lint/CDC/synthesis/STA checks, drive bug fixes, support sign-off, and collaborate with verification and cross-functional teams through silicon bring-up.

Lead and execute end-to-end IP/Subsystem verification for complex, multi-million-gate designs. Develop testplans and testbenches, run simulations and formal checks, drive verification methodology improvements, collaborate across design/DFT/mixed-signal teams, and support pre/post-silicon validation and emulation.

Lead IP/subsystem roadmap and architecture, design complex IPs for edge and automotive (ASIL-D), drive development from concept to silicon-quality IP, ensure quality/process improvements, mentor global teams, and collaborate across SoC/system functions.

Design and execute verification plans for memory controllers, interconnects and infrastructural IPs. Build scalable SystemVerilog/UVM environments, drive functional and code coverage targets, manage regressions, debug RTL/testbench issues, and own end-to-end IP verification sign-off while collaborating with design teams.

Lead physical implementation of IP/subsystem/IC from RTL synthesis to GDS. Perform floorplanning, routing, STA timing convergence, design ECOs, and physical verification to meet DRC/LVS, electromigration, and IR drop rules. Define physical design strategies per technology node and contribute to problem resolution and optimization.

Design and verify DFT features at subsystem and top levels: insert and verify MBIST, analyze/fix scan DRCs, run ATPG coverage and pattern generation, insert TAP/IO/test pinmux, perform power-aware RTL/GLS simulations, and support pattern bring-up with product and test teams.

Provide CAD support and methodology enablement for digital verification: troubleshoot simulation/regression/coverage flows, deploy and maintain EDA tools and CI/CD/regression systems, optimize compute/LSF environments, collaborate with DV/RTL teams and vendors, and deliver training, documentation, and automation for ASIC/SoC verification.

Lead end-to-end verification for complex IPs and subsystems, implement advanced verification methodologies, own verification quality metrics, drive coverage closure and defect prevention, improve verification flows, and collaborate with cross-functional global teams for pre/post-silicon validation.

Lead end-to-end verification for complex IPs and subsystems, driving first-pass silicon success through advanced verification methodologies, testbench development, coverage closure, defect prevention, and cross-functional collaboration across pre- and post-silicon validation.