Senior Design Engineer

Reposted One Month Ago
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Noida, Gautam Buddha Nagar, Uttar Pradesh, IND
In-Office
Senior level
Automotive • Internet of Things • Mobile • Semiconductor • Industrial
The Role
Lead physical implementation of IP/subsystem/IC from RTL synthesis to GDS. Perform floorplanning, routing, STA timing convergence, design ECOs, and physical verification to meet DRC/LVS, electromigration, and IR drop rules. Define physical design strategies per technology node and contribute to problem resolution and optimization.
Summary Generated by Built In

Senior DFT Engineer: You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs. You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.

 

Key Responsibilities

-Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).

-Develop and integrate scan insertion, test compression, and ATPG patterns.

-Implement memory BIST and logic BIST strategies.

-Collaborate with RTL and physical design teams for DFT insertion and timing closure.

-Perform DFT verification at RTL and gate-level simulations.

-Work with ATE teams for test program development and silicon bring-up.

-Optimize test coverage, pattern count, and test time.

 

Required Skills

-Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.

-Hands-on experience with industry standard ATPG tools.

-Proficiency in UPF/CPF-based low-power DFT.

-Knowledge of fault models (stuck-at, transition, path delay).

-Familiarity with physical design constraints for DFT.

-Experience in silicon debug and ATE bring-up.

 

Preferred Qualifications

- Pas experience with SoC level DFT

-Exposure to high-speed interfaces and DFT for mixed-signal blocks.

-Strong problem-solving and communication skills.

 

Education

-Bachelor’s or Master’s in Electrical/Electronics Engineering.

More information about NXP in India...

#LI-9415

Skills Required

  • Experience with RTL synthesis and GDS implementation
  • Expertise in floorplanning and routing for physical design
  • Proficiency in Static Timing Analysis (STA) and timing convergence
  • Experience with design ECO and physical verification workflows
  • Familiarity with DRC, LVS, electromigration, and IR drop checks
  • Ability to define physical design strategy across technology nodes
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The Company
HQ: Eindhoven
21,993 Employees
Year Founded: 2006

What We Do

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA

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