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Leads verification strategy and execution for complex semiconductor memory interface designs at block and system levels. Develops and optimizes SystemVerilog/UVM testbenches, test plans, coverage strategies, checkers, and constrained-random testing. Owns verification from planning through signoff, drives debugging and coverage closure, partners with RTL engineers, improves verification methodologies, and mentors verification engineers while communicating technical risks and readiness to leadership.

Provides technical leadership for verification of complex semiconductor memory interface designs. Defines verification strategies, test plans, coverage goals, and scalable SystemVerilog/UVM environments; drives constrained-random testing, functional coverage, debugging, coverage closure, and signoff. Partners with RTL and design teams to resolve issues, improve verification efficiency, and ensure functional and performance requirements are met. Mentors verification engineers and communicates technical risks, progress, and readiness to engineering leadership.

Provides technical leadership for semiconductor design verification at block and system levels. Defines verification strategies, test plans, coverage goals, and UVM environments; leads constrained-random testing, debugging, coverage closure, and signoff. Partners with RTL and design teams, develops reusable verification components, improves methodologies, and mentors engineers. The role focuses on next-generation DDR6 memory interface products and data buffer silicon.

Lead verification strategy and execution for complex semiconductor memory interface designs at block and system levels. Architect SystemVerilog and UVM environments, develop test plans, drive constrained-random testing, functional coverage, debugging, and coverage closure, and own verification through signoff. Collaborate with RTL and design teams, improve methodologies and reuse, resolve complex failures, mentor engineers, and communicate technical risks and readiness to stakeholders.

Manages foundry and fab activities including product and technology transfers, change control, safe launches, new product introductions, process improvement, quality investigations, customer RMAs, and foundry audits. Partners with foundries, quality teams, design, and process engineering groups to qualify changes, resolve root causes, improve process performance, and deliver semiconductor technologies against benchmark quality, cost, and cycle-time targets.

Six-month internship developing a graduation thesis in silicon validation automation for Power Management ICs. Responsibilities include designing laboratory test setups, developing Python-based validation frameworks and measurement scripts, validating analog, digital, mixed-signal, and power management ICs, analyzing test data, correlating results, preparing technical reports, and collaborating with cross-functional engineering teams.

Lead and mentor a seven-person analog design team developing advanced analog and mixed-signal ICs for automotive and industrial sensing products. Provide hands-on technical leadership across circuit architecture, design, verification, silicon validation, qualification, and production ramp. Own complex analog subsystems, establish engineering methodologies, conduct design reviews, collaborate with global engineering and product teams, and support recruiting and team growth.

Senior Manager, Application Engineering role at Renesas, an embedded semiconductor solutions provider serving automotive, industrial, infrastructure, and IoT markets. The provided description contains company information but no specific responsibilities or qualifications.

Supports semiconductor EDA flows, tools, design environments, regression testing, and automation scripts. Assists internal engineering users with technical investigations, analyzes test results, documents methodologies, and contributes to digital design activities such as synthesis, timing analysis, implementation, DFT, and verification. The role is designed for a new or recent graduate developing expertise in semiconductor design automation and EDA engineering while collaborating with global engineering teams.

Design and own analog layouts from block level through full chip for power-management products, including charge pumps, comparators, amplifiers, bandgaps, and regulators. Responsibilities include floorplanning, matching, electromagnetic and reliability design, die-level analog/digital and power integration, package connectivity, DRC/LVS flows, methodology development, and schedule ownership. The engineer may manage and mentor junior engineers while collaborating with circuit and layout teams.