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Design and validate high-speed digital, analog, and power hardware for server-class and embedded platforms. Responsibilities include architecture, schematic capture, circuit and signal integrity analysis, PCB coordination, board bring-up, debugging, system validation, documentation, and production readiness. The engineer collaborates with firmware, software, BIOS, device driver, mechanical, EMC, SI, and QA teams while using Cadence Allegro, Altium Designer, Python, and Perl.

Leads ASIC physical design for advanced-node silicon products, including floorplanning, partitioning, placement, clock-tree synthesis, routing, timing and signal-integrity closure, ECOs, power planning, and physical verification. Mentors engineers, leads block closure, interfaces with front-end ASIC teams, and applies low-power techniques such as voltage islands, power gating, and substrate biasing. Requires expertise with Cadence or Synopsys tools, PrimeTime, Perl, Tcl, and 7nm-or-smaller designs.

Develop ASIC and chip-level verification environments using SystemVerilog, UVM, C/C++, and scripting. Create verification plans, tests, assertions, coverage models, regression automation, and debug workflows to achieve tapeout readiness. Collaborate with architects, designers, and system engineers while validating hardware, software, and industry-standard protocols. Experience with simulators, waveform/debug tools, formal verification, and processor platforms is valuable.

Develop ASIC and chip-level verification environments using SystemVerilog, UVM, C/C++, and scripting. Create verification plans, tests, assertions, coverage models, regression automation, and debug workflows to achieve tapeout readiness. Collaborate with architects, designers, and system engineers while debugging software and hardware issues. Experience with simulators, formal verification, industry protocols, and processor platforms is advantageous.

Develops and manages design-for-test solutions for complex multi-million-gate SoCs, including Scan and MBIST for mixed-signal IP. Oversees test tool development, semiconductor design and manufacturing activities, silicon bring-up, debugging, and cross-functional hardware, firmware, and software integration. Leads global teams, develops managers and individual contributors, manages schedules and risks, and delivers quality semiconductor products within cost and time-to-market objectives.

Leads DFT and test development for complex multi-million-gate SOCs with mixed-signal IP. Defines scan, MBIST, and ATE solutions across the SOC design and manufacturing lifecycle, including RTL, synthesis, implementation, timing, verification, characterization, and silicon bring-up. Manages technical teams, tool development, software-related tasks, global collaboration, project execution, risk, quality, cost, and schedules.

Manages contract workforce profitability by evaluating candidates, reviewing costs and margins, tracking utilization, validating vendor invoices and timesheets, supporting rate negotiations, and preparing monthly MIS reports. Coordinates with HR, Sales, and Finance to control contractor deployment, billing, budgets, and commercial terms. Recommends contractor continuation, redeployment, replacement, or exit based on financial performance.

Generate and qualify outbound leads across India through email sequences, LinkedIn outreach, and cold calling. Use sales intelligence and CRM tools to nurture prospects, understand customer pain points, and communicate qualified opportunities to field sales teams. The role requires explaining embedded and digital engineering solutions in business terms, collaborating with sales colleagues, and working in a target-driven environment.

Lead ASIC design engineer responsible for RTL and logic design, complex SoC design and integration, multi-clock and asynchronous interface development, and ASIC verification activities. The role uses Verilog/SystemVerilog, lint and CDC tools, synthesis, timing analysis, ECO fixes, formal verification, and AMBA protocols including AXI, AHB, and APB. Strong communication, collaboration, creativity, and initiative are required.

Design complex, high-density, high-speed analog, digital, RF, and mixed-signal PCBs for server-class and HDI platforms. Create libraries and footprints, establish electrical constraints, route high-speed interfaces, design power supplies, and address power integrity, thermal, and reliability requirements. Generate and validate manufacturing data, manage PCB-to-mechanical conversions, and support release processes. Collaborate with signal and power integrity, mechanical, manufacturing, DFM/DFA, and CAD teams using major PCB design tools.