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Internship focused on automated testing of Silicon Labs Wi-SUN wireless products. The intern will collaborate with the Budapest Quality Assurance team, develop Python programming skills, use an internal Python test framework, deepen wireless communication knowledge, and learn to apply AI effectively. The role is part-time, 20–25 hours per week, with flexible hours and a January start.

Defines and drives the digital IP portfolio roadmap, aligning product needs, architecture, design, applications, customers, and industry standards. Prioritizes IP development opportunities, coordinates global IP teams, manages change processes, evaluates technical feasibility and tradeoffs, and builds cross-functional alignment. The role requires deep semiconductor and RTL design experience, strong SoC knowledge, and the ability to guide roadmap decisions across a portfolio of more than 200 IPs.

Lead and manage the Software Quality Assurance function: define test strategy, establish QA processes and metrics, oversee test automation and CI/CD integration, coordinate with engineering and product teams to ensure release quality, mentor and grow the QA team, and manage hiring and resource planning.

Develop and maintain Python/Pytest automated tests for embedded wireless products, focusing on Bluetooth Low Energy features. Own test planning, strategy, coverage, CI execution, debugging, root cause analysis, and quality improvements. Collaborate with developers, product managers, application engineers, and global QA teams to resolve defects and communicate testing risks. The role also uses AI-assisted development tools, supports continuous integration, and validates firmware and embedded products.

Develop timing constraints and signoff methodologies for low-power wireless SoCs and IP. Improve static timing analysis flows, establish timing criteria, analyze reports using scripting, and drive timing closure across global design and multifunctional teams. The role addresses complex clocking, timing corners, aging, on-chip variation, signal integrity, mixed-signal IP integration, and functional and test modes.

Lead hardware product management for IoT wireless SoCs from concept through product definition and customer alpha. Define requirements, features, specifications, system KPIs, evaluation tools, and product roadmaps across wireless protocols and embedded technologies. Collaborate with IC design, software, validation, test, marketing, applications, operations, and sales teams. Conduct competitive and die-level analysis, develop technology investment business cases, manage product portfolios, and present strategic recommendations to executives.

Leads verification of complex digital RTL blocks for wireless modem baseband and PHY-layer IPs. Develops SystemVerilog/UVM environments, testbenches, verification plans, constrained-random tests, coverage models, and C-based reference-model integrations. Performs bit-exact verification, debugs RTL and testbench issues, verifies mixed-signal datapaths, and collaborates with design, systems, and SoC teams to resolve integration challenges and deliver reliable wireless SoCs.

Design and develop synthesizable RTL for wireless modem digital baseband and PHY-layer IPs. Define microarchitecture, implement DSP blocks, optimize power, performance, and area, and support verification, synthesis, lint, CDC, RDC, integration, and debugging. Collaborate with modem systems, verification, analog, and SoC teams to deliver high-quality wireless IPs for Wi-Fi and low-power IoT devices.

Plans and executes wafer fabrication, assembly, and test operations across outsourced semiconductor manufacturing partners. Manages production schedules, supplier performance, inventory, SAP and APS planning data, customer commitments, supply risks, and recovery plans. Collaborates cross-functionally on demand planning, procurement, logistics, quality, new product introductions, product transfers, and process improvements.

Provides technical leadership for complex wireless SoC development from product definition through architecture, design, integration, verification, tapeout, silicon bring-up, validation, and production. Owns chip-level technical decisions, execution planning, risk management, design closure, and cross-functional coordination. Leads resolution of architectural, implementation, and silicon issues while ensuring functional, performance, power, area, cost, and quality objectives are achieved.