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Seeking a Senior Memory Design Engineer to develop custom SRAM memories, Register file memories, and compiled memories, optimize power and performance metrics, and support silicon bring up. Responsibilities involve circuit design, simulation, equivalence checking, PPA analysis, and collaboration with cross-functional teams.

As a Memory Controller Verification Engineer, you'll verify the digital logic aspects of DDR and HBM memory subsystems, develop test plans and testbenches, integrate verification IPs, and collaborate with design teams and third-party vendors. You'll also engage in debugging and regression activities, ensuring robust memory interface performance.

The Silicon Physical Design Verification Manager will develop PDV methodology and infrastructure for verifying large SoCs, ensuring quality integration across design teams and driving convergence at both full chip and sub-block levels, while managing a team of engineers to meet project milestones.

Seeking experienced UPF experts to build and validate IP/SOC level power intent definitions for high performance power efficient SOC designs. Responsible for bringing up power intent checking flows, debugging issues, and optimizing for low power. Requires strong communication, interpersonal skills, and scripting abilities in Tcl and Python.

Seeking a Senior Memory Design Engineer with 10 years of custom circuit design experience to drive the design and development of SRAM, register file, and custom cells for high performance and low power designs. Responsibilities include working with microarchitecture team, conducting PPA analysis, design equivalence checking, collaborating with CPU and SoC physical design teams, and interacting with technology and CAD teams.

Responsible for internal interconnect architecture specification and performance optimization. Collaborate with Silicon team members and industry consortiums. Develop, assess, and refine architecture to meet power, performance, and timing goals.

Positions are open for full-time in the areas of DFT design from unit level to chip level, involving all aspects of DFT design functions from scan, MBIST, to ATPG. Roles in the areas of CPU and SOC DFT design and verification.