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The Sr. SLT engineer will develop and execute test programs for Silicon, focusing on test hardware design, product characterization, process improvement, and manufacturing support.

The role involves developing test programs for various device types on ATE, conducting test hardware bring-up, and collaborating for optimal debugging and test strategies.

The SoC Fabric Architect will define and optimize fabric architectures, collaborate with multi-disciplinary teams, and analyze trade-offs for system performance and power goals.

Develop and optimize power modeling for CPU and SoC blocks, analyzing trade-offs and collaborating with various teams to enhance design methodologies.

As a SoC Performance Modeling Engineer, you will design and implement performance models, validate them, analyze performance studies, and enhance modeling infrastructure.

The SoC Performance Modeling and Verification Engineer will validate performance models against specifications, develop test suites, and debug performance issues in Rivos SoCs, collaborating with architecture teams.

Responsible for automating formal verification flow, collaborating with design teams, and improving tools for logical equivalence checks.

The Quality and Reliability Engineer ensures products meet reliability standards, conducts testing, identifies weaknesses, and collaborates with teams to enhance product reliability.

Responsible for verifying DDR and HBM memory subsystem designs, developing test plans, integrating IPs, and supporting debug efforts across teams.

The engineer will verify features of DDR and HBM memory subsystems, develop test plans and testbenches, and support debug processes.