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Lead workload and silicon-level performance analysis for next-generation server platforms (AI at scale and HPC). Define metrics and benchmarks, build microbenchmarks, identify bottlenecks, recommend architectural optimizations, and collaborate with hardware and software teams to validate improvements end-to-end.

Drive SoC and server platform performance by characterizing real-world AI/HPC workloads on production silicon, designing microbenchmarks, diagnosing bottlenecks, and translating findings into architectural and system-level optimizations while collaborating with hardware and software teams.

The role involves developing perception systems for robotics, integrating them with planning and control systems, and evaluating performance under constraints.

Provide strategic commercial legal support for semiconductor and silicon hardware transactions. Draft and negotiate complex contracts (master purchase, partnerships, multi-year customer deals), advise executives, manage risk (liability, indemnification, IP, warranties), mentor other lawyers, and build scalable legal processes and playbooks for high-value deals with hyperscalers and enterprise customers.

Develop and automate end-to-end multi-die sign-off flows for timing, power, thermal, IR/PDN, and yield. Integrate EDA tools, statistical/ML algorithms, and distributed processing to optimize power/performance and lead product-level implementation and sign-off with design teams, foundries, and partners.

Lead the development of next-generation system architectures, drive technology objectives, and collaborate with teams to ensure alignment in product goals.

As a SoC Emulation Engineer, you'll develop verification testbenches, modify RTL for SoC, and collaborate to define future architectures.

The Principal High-Speed I/O Architect designs interconnect architectures for SoCs, collaborating on performance and efficiency in various markets.

As a Performance Analysis Engineer, you will analyze SoC performance, identify bottlenecks, collaborate with architects, and develop testing workflows.

Develop and maintain high-performance C++ models of Arm Interconnect IP for system-level simulation. Investigate and resolve modeling and integration issues, deliver incremental model updates, collaborate with architects and hardware engineers on evolving designs, integrate and debug software on Arm Virtual Platforms, and drive technical discussions to improve modeling workflows.