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3 Days AgoSaved
Hybrid
San Jose, CA, USA
145K-197K Annually
Mid level
145K-197K Annually
Mid level
Artificial Intelligence • Internet of Things • Semiconductor
Manage and execute developer-facing grassroots programs (meetups, workshops, hackathons). Coordinate logistics, timelines, communications, cross-functional partners, and post-event follow-up. Turn goals into action plans, identify and resolve blockers, and improve repeatable processes to strengthen operational execution.
Reposted 3 Days AgoSaved
Hybrid
Austin, TX, USA
198K-268K Annually
Mid level
198K-268K Annually
Mid level
Artificial Intelligence • Internet of Things • Semiconductor
The role involves managing safety and cybersecurity for automotive SoC programs, ensuring compliance with standards, and improving development processes.
Top Skills: AspiceIec 61508Iso 26262Iso/Sae 21434
Reposted 3 Days AgoSaved
Hybrid
Chandler, AZ, USA
198K-268K Annually
Senior level
198K-268K Annually
Senior level
Artificial Intelligence • Internet of Things • Semiconductor
As a Staff Signal and Power Integrity Engineer, you will develop and analyze System-in-Package designs, enhance Arm IP performance, and lead technical oversight for related projects.
Top Skills: Ansys SuiteCadenceLinux
Reposted 3 Days AgoSaved
Hybrid
Austin, TX, USA
250K-338K Annually
Mid level
250K-338K Annually
Mid level
Artificial Intelligence • Internet of Things • Semiconductor
The Principal Machine Learning Engineer will develop ML algorithms and optimize performance on ARM computing platforms, collaborating across hardware, software, and ML algorithms, while focusing on performance, power, and area.
Top Skills: PythonPyTorchTensorFlow
Reposted 3 Days AgoSaved
Hybrid
San Jose, CA, USA
284K-384K Annually
Senior level
284K-384K Annually
Senior level
Artificial Intelligence • Internet of Things • Semiconductor
The Senior Director of Finance will lead financial strategy, revenue forecasting, P&L management, and decision support for Arm's Cloud AI Business Unit, partnering closely with sales and product teams to manage complexity and drive growth.
Top Skills: Ai InfrastructureCloud InfrastructureEnterprise HardwareFinancial ModelingP&L ManagementRevenue ForecastingScenario AnalysisSemiconductor
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Reposted 3 Days AgoSaved
Hybrid
Austin, TX, USA
309K-418K Annually
Expert/Leader
309K-418K Annually
Expert/Leader
Artificial Intelligence • Internet of Things • Semiconductor
Define and analyze SoC system performance requirements, engage with teams to optimize performance, and drive technology roadmaps for compute infrastructure.
Top Skills: EmulationFpgaPcieRtl SimulationSocSystem Architecture
Reposted 3 Days AgoSaved
Hybrid
Austin, TX, USA
162K-219K Annually
Mid level
162K-219K Annually
Mid level
Artificial Intelligence • Internet of Things • Semiconductor
The Architect will improve Arm's hardware acceleration infrastructure through benchmarking, scheduling optimization, vendor API integration, and performance visualization, enhancing overall productivity.
Top Skills: BashEdaFpgaGrafanaLinuxPrometheusPython
Reposted 3 Days AgoSaved
Hybrid
Chandler, AZ, USA
198K-268K Annually
Senior level
198K-268K Annually
Senior level
Artificial Intelligence • Internet of Things • Semiconductor
The experienced SIPI engineer will lead design and analysis of System-in-Package designs, improve power delivery techniques, and ensure electrical integrity while collaborating with global teams.
Top Skills: Ansys SuiteCadenceLinuxPythonSkill
Reposted 5 Days AgoSaved
Hybrid
San Jose, CA, USA
212K-286K Annually
Senior level
212K-286K Annually
Senior level
Artificial Intelligence • Internet of Things • Semiconductor
The Product Manager for AI Infrastructure will lead performance analysis, inform product roadmaps, and drive alignment across teams for AI compute platforms.
Top Skills: Ai Compute PlatformsComputer EngineeringData Center Ai WorkloadsElectrical EngineeringMl Accelerators
6 Days AgoSaved
Hybrid
Austin, TX, USA
162K-219K Annually
Senior level
162K-219K Annually
Senior level
Artificial Intelligence • Internet of Things • Semiconductor
Design and integrate SoC subsystems (PCIe, DDR/LPDDR, HBM, UCIe, Ethernet); author micro-architecture specs; develop RTL in Verilog; perform static checks (CDC, RDC, X-Propagation, linting); collaborate with verification, performance analysis, and backend teams for floorplanning and timing closure; improve design methodologies and mentor team members while supporting project management.
Top Skills: ArmCdcDdrDftEEthernetFloorplanningHbmLintingLpddrOvmPciePerlPythonRdcRtlSynthesisSystemverilogTiming AnalysisTiming ClosureUcieUvmVerilog HdlX-Propagation
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