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Lead Americas sales P&L and GTM across wearables, IoT, healthcare, and consumer electronics. Build and scale a regional sales organization, drive strategic OEM/ODM partnerships, manage channel and distribution, align cross-functionally to accelerate design wins, and deliver revenue against annual targets.

Lead development, testing, and maintenance of Ambiq's Zephyr software offering: port SoCs, enable hardware platforms, build drivers and samples, manage CI/CD and issue resolution, optimize for ultra-low power, create application notes, and support field/customers.

Own strategic global Tier‑1 customer relationships on the East Coast: drive account plans, forecasting, design wins, and cross‑regional program execution while engaging ODMs and executive stakeholders to expand Ambiq's ultra‑low‑power solutions.

Lead strategic global customer relationships for Ambiq, owning account strategy, forecasting, and executive engagement. Gather customer and competitive intelligence, collaborate with ODMs and ecosystem partners, drive design wins and revenue growth, and expand into new verticals while ensuring cross-functional alignment.

The Principal Embedded Software Architect will design the software architecture for low-power Edge AI MCUs, leading decisions for functionality and performance, partnering with hardware teams, and mentoring engineers.

The Sr. Director of Front End Engineering will drive innovation in semiconductor solutions, oversee engineering teams, and ensure project success with customer-centric solutions.

As Head of Post-Silicon Engineering, define strategies for low-power MCUs, lead validation, manage global engineering teams, and engage with customers for product development.

Develop, extend, and test secure bootrom/bootloader and related SDK components for Apollo SoC. Perform pre-silicon FPGA emulation, post-silicon bring-up, cryptographic hardware-accelerated testing, HAL/BSP implementation, and collaborate on test automation and security verification.

Lead end-to-end timing methodology and signoff for SoCs: define flows, constraints, and PVTR corners; drive block-to-SoC timing closure and pre-/post-silicon correlation; perform extraction, glitch/noise and power/timing tradeoff analysis; automate STA workflows and collaborate with RTL, DFT, PnR, IP, bring-up, and validation teams.

The Field Application Engineer will support global customers in design-in activities, develop product solutions, optimize power consumption, and assist with customer HW/SW development.