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Lead timing methodology and closure for block and SoC levels in modern FinFET/multi-patterning processes. Define flows, constraints, signoff correlation, timing margining, glitch noise analysis, and collaborate with RTL, PnR, DFT, and post-silicon teams to achieve timing convergence and best-in-class PPA.

Lead software architecture for low-power Edge AI MCUs: define requirements, perform functional allocation, prototype, guide implementation and testing, optimize performance/power, enforce standards, and mentor engineers.

The Principal Engineer - RTL will oversee pre-tape out quality for digital SoC modules, lead architecture and micro-architecture development, and manage RTL development. Responsibilities include IP integration, collaboration with verification teams, and assisting in silicon validation.

Responsible for verifying digital and mixed-signal designs including systems-on-chip, developing test plans, automating testing, and collaborating with various teams to ensure design verification for low-power applications.

Lead the development of embedded software platforms for ARM Cortex-M MCUs, ensuring high-quality releases, mentoring teams, and driving cross-functional alignment.

The Office Operations Manager oversees daily office operations, ensuring a well-functioning workspace, manages office logistics, engages employees, and coordinates events while supporting the HR team.