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Lead development, integration, optimization, and validation of GPU hardware abstraction layers and graphics software stacks for embedded Ambiq MCUs. Responsibilities include OpenGL ES and vector graphics middleware, display integration, UI frameworks, performance and power optimization, example applications, testing, FPGA pre-silicon verification, post-silicon bring-up, and hands-on hardware/software debugging.

Leads architecture, development, testing, debugging, profiling, and optimization of SDK power-management software for low-power ARM Cortex-M MCUs. Responsibilities include clock and memory management, low-power modes, RTOS ports, power modeling, system-level optimization, technical reviews, cross-functional issue resolution, and mentoring. The role requires hands-on embedded firmware development and technical leadership across hardware, software, validation, and vendor teams.

Leads system-level test strategy, regression framework development, embedded test implementation, laboratory instrumentation automation, and root-cause debugging for MCU platforms. The role supports FPGA, emulation, and post-silicon validation, improves test reporting and traceability, collaborates with global hardware and software teams, and mentors engineers on automation, debugging, and test quality.

Provides technical leadership for embedded MCU software development focused on Secure Boot ROM, secure bootloaders, SDK security, cryptographic operations, HAL, and BSP development. Leads security feature implementation from design through production, including FPGA and silicon testing, debugging, automated testing, and cross-functional collaboration. Requires deep expertise in ARM architectures, bare-metal and RTOS systems, embedded security, C/C++, Python, and low-level hardware/software debugging.

Leads architecture, specification, transistor-level design, verification, layout supervision, validation, and production release of complex analog and mixed-signal IC subsystems. The role addresses power management, clocking, data conversion, advanced-node design, manufacturing test, and post-silicon characterization. It also guides senior engineers, leads technical reviews, resolves cross-functional issues, and supports product development and customer problem resolution.

Own revenue and product margin planning, forecasting, and budget-to-actual analysis for semiconductor products and manufacturing operations. Build financial models and R&D investment business cases, including ROI, payback, and sensitivity analyses. Partner with Sales, Marketing, R&D, Manufacturing, Operations, Accounting, and executives to optimize margins, prioritize investments, explain financial performance, and support investor relations. The role includes periodic travel to Taiwan and occasional late-night calls.

Lead system architecture for next-generation ultra-low-power AI SoCs from concept through production. Define processor, memory, interconnect, clocking, power, accelerator, and hardware/software partitioning strategies while managing power, performance, and area tradeoffs. Develop architecture specifications and models, evaluate IP, guide silicon implementation and validation, collaborate with customers and cross-functional engineering teams, and mentor architecture staff.

Responsible for post-silicon validation and characterization of analog and mixed-signal SoC subsystems. Develop validation plans, automate testing and data analysis, characterize silicon across process, voltage, and temperature, analyze performance, correlate results with simulation and production data, and debug analog, digital, firmware, power, and board-level interactions. The role also supports validation hardware, lab infrastructure, test coverage, yield improvement, and production readiness.

Designs and develops PCB-based evaluation hardware for low-power, ARM-based SoCs. Responsibilities include hardware architecture, schematic and layout design, system bring-up, lab debugging, manufacturing test development, customer hardware reviews, issue resolution, embedded software support, and creation of application notes and hardware design guidelines.

Own end-to-end digital design verification for complex SoCs at block, subsystem, and full-chip levels. Develop UVM/SystemVerilog testbenches, verification plans, constrained-random and directed tests, scoreboards, coverage models, and C/C++ SoC validation libraries. Automate regressions and reporting, debug failures, perform root-cause analysis, and collaborate with architecture, design, and software teams. The role requires managing verification milestones, risks, and deliverables through multiple successful tape-outs.