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Leads automated place-and-route and physical design from floorplanning through GDSII tapeout. Develops scripting-based automation for timing and design closure, data extraction, QoR monitoring, ECOs, and physical verification. Oversees floorplanning, power planning, placement, routing, clock tree synthesis, timing and signal integrity analysis, design signoff, and LEC/CLP checks. Collaborates with cross-functional engineering teams to improve design flows, methodologies, quality, and productivity.

Develop and execute global strategic sourcing strategies, manage supplier relationships and contracts, negotiate pricing, reduce costs, assess supplier capabilities, mitigate supply risks, and support product development and launches. The role partners with engineering and cross-functional teams, drives procurement process improvements, analyzes markets and spend, and manages sourcing activities across international suppliers. Approximately 20% domestic and international travel is required.

The Principal Engineer in Physical Design will lead full chip physical implementation, focusing on APR and managing design complexities, while collaborating with global teams.

The Engineering Planner coordinates engineering projects, manages inventory, supports build plans, and collaborates with various teams to ensure material availability and effective communication.

Leads strategic product marketing, product line strategy, roadmap development, business growth, customer engagement, competitive positioning, and sales enablement for embedded semiconductor security solutions. Builds strategic customer relationships, drives design wins and revenue growth, translates market and customer needs into product investments, presents technical value propositions, supports account planning, and collaborates globally across engineering, product management, applications, sales, and marketing teams.

Leads the firmware engineering team for FlashTec storage products, overseeing architecture, development, integration, validation, release, project planning, and risk mitigation. Partners with hardware, ASIC, validation, systems, product management, and customer engineering teams. Develops managers and engineers, advances Agile practices, resolves complex firmware issues, and contributes to storage technology roadmaps while fostering innovation, quality, and continuous improvement.

Drive semiconductor product support and new product development from design through mass production. Coordinate cross-functional engineering, applications, quality, suppliers, foundries, and assembly partners; manage validation, characterization, qualification, and material control plans; develop burn-in hardware and software; analyze yields and test data; resolve manufacturing issues; support product migrations; and improve quality, cost, delivery, and production capacity.

The Physical Design Engineer will implement complex mixed signal designs, optimize floorplans, perform timing analysis, and collaborate with cross-functional teams.

Manages documentation, part-number creation, engineering work orders, procurement requests, material tracking, and production-release activities for new semiconductor products. Coordinates wafer, probe, assembly, testing, qualification, and manufacturing activities across engineering, fabs, suppliers, and international backend teams. Maintains accurate product data and communicates with cross-functional stakeholders to support timely product introduction and manufacturing readiness.

Develop and support semiconductor physical verification flows, rule decks, regression tests, and PDKs across multiple process technologies. Use Calibre, Pegasus, or Hercules for DRC, LVS, PERC, ERC, extraction, and related verification. Debug physical verification issues, automate procedures, enhance foundry decks, support layout and design engineers worldwide, and collaborate on DRC rules, design-for-manufacturing checks, quality, reliability, and yield improvements.