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Lead triage and resolution of hardware, firmware, and software vulnerabilities across semiconductor products; perform technical assessments (CVSS), coordinate remediations and disclosures, author advisories, run SBOM/VEX analysis, and support regulatory and standards readiness (CRA, IEC 62443, ISO/SAE 21434) across engineering and compliance teams.

Provide cybersecurity engineering and architecture for mission and enterprise systems, translate NIST/CNSS controls into secure designs, troubleshoot Linux/Windows servers and endpoints, Cisco network devices, and enterprise storage, implement continuous monitoring (vulnerability scanning, SIEM), perform technical security assessments using Tenable and DISA STIGs, prioritize risk, and lead remediation efforts to maintain compliance and mission assurance.

Lead product security governance across business units: define frameworks for threat modeling, vulnerability management, regulatory readiness, and supply-chain security; drive cross-functional adoption, metrics, executive reporting, and industry engagement.

The Senior Engineer II is responsible for product reliability, qualification tests, and root cause analysis for FPGA products, collaborating across teams to ensure quality and compliance throughout the product lifecycle.

Manage a team of Supply Chain Buyers ensuring the flow of materials into Microchip Technology's fabs. Responsibilities include sourcing, contract negotiations, performance evaluation, and coordination of procurement activities.

Lead the product engineering team in the development and introduction of new FPGA and SoC products, oversee qualification, enhance yields, and support customer needs.

The role involves leading new product introductions, providing technical support on the manufacturing line, performing failure analysis, and supporting the product lifecycle in the Frequency and Time Systems team.

Provide advanced pre- and post-sales FPGA/SoC consulting and support to tier1 customers: design/debug FPGA/SoC systems, develop reference designs, perform timing-closure and board-level reviews, train field engineers, and create customer-facing collateral.

Lead development and scaling of RTL-to-silicon implementation methodologies for 12nm hierarchical SoCs and multi-die designs. Own synthesis, UPF-based low-power flows, timing convergence, constraint development, floorplanning collaboration, and mentor teams to ensure predictable signoff and first-generation product readiness.

Lead design, develop, test, deploy, and support custom enterprise applications, reporting, and ETL for manufacturing and engineering. Serve as technical lead, mentor team members, create documentation, manage projects, support multiple global sites, and supervise staff at the Colorado Springs FAB5 facility.