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Design and implement idiomatic Python APIs and bindings for CUDA Core Libraries, develop and integrate native C/C++ components, define interoperability boundaries (Python, C/C++, Rust), optimize performance, own feature lifecycle (design through maintenance), and collaborate with compiler, runtime, and user teams to ensure correctness, usability, and performance.

Architect and develop system software for NVIDIA Halos across QNX, Linux, and hypervisor environments. Design BSP, boot, drivers, I/O virtualization, and platform software for NVIDIA SoCs. Build safe, secure mixed-criticality systems compliant with ISO 26262/21434, employ formal methods and AI-assisted engineering tools, and optimize platform performance and diagnostics.

Develop algorithms and optimizations for inference and compiler stack, enhance performance metrics, collaborate with hardware teams, and publish work on novel approaches.

Develop and implement compiler optimization algorithms for deep learning workloads, analyze networks, debug and profile GPU performance (CUDA), define public APIs, and deliver ahead-of-time and just-in-time compilation techniques for NVIDIA GPUs to improve inference performance, build times, and memory efficiency.

Design and implement RTL and system-level SoC modules, perform logic synthesis and timing analysis, integrate modules into SOC, collaborate with architects and verification teams, support silicon bring-up, and improve design flows and methodologies to enhance efficiency and chip yield.

Verify GPUs by testing unit levels and contributing to verification methodologies. Collaborate with architecture teams to refine microarchitecture and support validation.

Architect and develop automated flows using C++ and Python. Collaborate on methodologies for chip builds, integrating with VLSI teams to resolve challenges.

The role involves optimizing CUDA kernels for geometric neural networks, building interfaces for PyTorch and JAX, and collaborating with research teams to develop GPU-accelerated software for scientific applications.

The role involves developing device drivers for network interface cards, optimizing software solutions, and addressing complex technical issues in the Linux kernel group.

Lead development of DFT power, thermal, and voltage-noise methodologies for datacenter GPUs. Drive post-silicon power/thermal analysis, deploy DFT solutions using applied ML/GenAI, partner with product and power architecture teams, and mentor junior engineers on test designs, trade-offs, and silicon bring-up on ATE/SLT platforms.