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Design, develop, validate, and debug Tegra Boot and security firmware across automotive, embedded, and data center SoC platforms. Participate across the silicon lifecycle from pre-silicon simulation to silicon power-on, collaborate with hardware and software teams, and apply secure-boot, cryptography, and defensive programming practices to ship robust embedded firmware.

As a Senior Firmware Engineer, you will design, implement, and maintain firmware, optimize code paths, and collaborate with various teams to integrate systems and resolve issues in complex hardware interactions.

The role requires coordinating with stakeholders in the semiconductor industry to manage hardware programs, ensuring they align with company goals and methodologies while developing complex ASIC projects.

Design and implement DFT solutions (test access, IO and memory BIST, scan compression), develop DFT methodologies, validate test patterns on multi-million gate designs, support silicon bring-up/ATE debug, collaborate with RTL/STA/PNR teams, and mentor junior engineers. Scripting for automation in Perl/Python/Tcl.

The role involves developing scalable systems for physical design and quality checking of graphics processors, building automated flows, and collaborating with design teams to enhance methodologies and standards.

The role involves validating clocking structures in products, developing test plans, automation, and partnering with design teams to ensure high-quality verification of ASIC designs.

The role involves developing and deploying internal infrastructure tools for ATE test vector release, supporting silicon bringup, and debugging existing code. Candidates are expected to have extensive experience with ATE systems and strong scripting abilities, particularly in Perl and Python.

Lead and execute IT and security audits of manufacturing systems and external partners, assess third-party IT risk (foundries, OSATs, ODMs), review network, access controls, APIs and data exchanges, validate data integrity into data warehouses using analytics, and produce executive audit reports while driving remediation and managing on-site partner coordination and Tier-3 escalations.

As a Senior Memory System Engineer, you'll analyze memory technologies, collaborate with various engineering teams, and design memory architectures for NVIDIA SOCs.

Lead performance and scalability characterization of the DGX Cloud stack across Kubernetes and NVIDIA components. Design automated workload tests, build monitoring and CI/CD frameworks, triage large-scale Kubernetes issues, collaborate with researchers and upstream open-source communities, and present findings externally.