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Lead development of DFT power, thermal, and voltage-noise methodologies for datacenter GPUs. Drive post-silicon power/thermal analysis, deploy DFT solutions using applied ML/GenAI, partner with product and power architecture teams, and mentor junior engineers on test designs, trade-offs, and silicon bring-up on ATE/SLT platforms.

Lead robotics training data strategy: define formats and quality standards, oversee data collection/annotation, partner with researchers and external providers, build data acquisition plans, and deliver large-scale datasets and tooling to support robotics foundation models.

Lead invention of AI-driven ASIC development methodology, identify cross-stage bottlenecks, build scalable data pipelines, define metrics, mentor engineers, and evaluate AI/EDA research to improve predictability and cycle time.

Own and implement DFT architectures and test access mechanisms (IEEE standards, memory BIST, scan, memory dump, DFX security); architect and deploy DFT methodologies across RTL, verification, and pattern generation; collaborate with timing, physical design, software, bringup and production teams; perform silicon debug and ATE bring-up; mentor junior engineers on test design trade-offs.

As a CPU Performance Architect, you'll innovate CPU performance through microarchitecture, model improvements, resolve timing and power issues, and collaborate with teams. The role demands over 16 years of experience in CPU projects and strong advocacy and critical thinking skills.

Lead the architecture and delivery of high-scale web products across frontend and backend services, mentoring engineers, and improving code quality. Collaborate to enhance AI infrastructure for efficient research management.

Design and implement new features for high-performance CPUs and GPUs in an optimizing compiler. Collaborate with application teams to solve compilation and optimization problems, partner with colleagues on HPC-focused projects, and engage with open-source communities to advance compiler capabilities.

The role involves building and modernizing the RTL-to-GDS flow infrastructure for semiconductor design, improving EDA tool automation, and ensuring system resilience while debugging and collaborating with design teams.

Lead design and deployment of advanced silicon test methodologies, own cross-functional implementation of scan, BIST, and scan compression, and drive chip bring-up from pre-silicon to production. Develop standardized bring-up processes, mentor junior engineers, collaborate with VLSI and product teams, and validate test patterns and debug silicon failures.

Provide advanced support and root-cause analysis for NVIDIA networking technologies in AI clusters. Reproduce and resolve customer issues, develop fixes and tools, analyze performance/tuning for high-performance lossless networks, collaborate with R&D and customers, and occasionally support outside regular hours.