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Designs and reviews NVIDIA GPU and Tegra-based product boards across servers, automotive, robotics, industrial, and consumer applications. Collaborates with architects and cross-functional teams to optimize cost, performance, and schedules; prepares manufacturing documentation; develops improved circuits and functions; and enhances design workflows. Requires extensive board design experience, PCB review expertise, laboratory measurement skills, Linux and Windows proficiency, and strong communication abilities.

Develop and deploy NVIDIA reference AI supercomputer datacenter designs with cloud service providers and ODM partners. Provide technical guidance on server architecture, power, cooling, thermal, electrical, mechanical, manufacturing, testing, debugging, and datacenter integration. Create enablement plans, resolve complex system issues, support product roadmaps, coordinate cross-functional programs, and communicate status and trade-off recommendations across internal teams and industry partners.

Responsible for technical engagement with automotive partners, driving the adoption of NVIDIA's technology, managing relationships, and supporting software integrations.

The Senior Manager, Robotics Quality Assurance will lead test engineering strategy, automation development, and validate models for robotics products, ensuring quality across hardware and software.

Design and implement GPU performance analysis and profiling capabilities for NVIDIA hardware, drivers, and SDKs. Analyze chip features, prototype and refine data collection methods, collaborate with architects and developer tools engineers, and ensure observability of critical performance behaviors for next-generation GPUs and SoCs.

Lead architecture and development of Vehicle and Sensor Abstraction Layers (VAL/SAL) for autonomous vehicles. Manage teams building low-latency C++ systems with GPGPU (CUDA) acceleration, interfacing sensors and actuators, ensuring scalable integration, safety-compliant automotive software (MISRA), and validating via real-world and synthetic testing. Oversee in-vehicle tests, data analysis, unit testing, documentation, and cross-functional collaboration to deliver production-quality autonomy software.

The role involves designing and maintaining verification environments, developing test plans, creating UVM components, launching regressions, and collaborating with engineers to ensure high-quality IP delivery.

As an EDA Workflow Optimization Engineer, you will optimize and enhance workflows for chip development, working with teams to investigate, debug, and innovate tools for efficient engineering processes.

Design and develop a C++-based system for simplifying and accelerating computing in DL and HPC, alongside evaluating performance and improving library quality.

Lead CPU performance verification strategy, develop microbenchmarks and test plans, analyze workloads and benchmarks, identify bottlenecks, build performance-analysis infrastructure, and guide junior engineers. Collaborate with CPU architects and design engineers to validate microarchitectural features and correlate performance across sophisticated CPU designs.