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The engineer will innovate DFX Power methodologies, focus on low power & thermal solutions, work on data analysis and mentor junior engineers.

Design and develop software solutions for data center servers, focusing on Linux kernel modifications, device drivers, and system optimizations while directly collaborating with Cloud Service Providers.

The role involves timing analysis and closure for custom circuit designs, collaborating with teams to improve timing flows and models, validating designs, and addressing complex timing challenges in circuit layouts.

As a Senior ASIC Design Engineer, you will design and implement micro-architecture, collaborate with teams, develop RTL designs, and conduct functional verification.

Own reliability and continuous improvement of production-critical failure analysis systems; design scalable automation, data pipelines, analytics, and orchestration; apply AI/ML to accelerate root-cause analysis; partner with cross-functional semiconductor, CAD, and manufacturing teams; ensure operational excellence for large-scale production environments.

The role involves bridging architecture and design, analyzing power trade-offs, and improving power efficiency for CPU cores, with a focus on AI and HPC workloads.

The role involves researching, designing, and implementing advanced storage solutions for HPC workloads, optimizing for performance, cost, and scalability across cloud infrastructures, while automating management processes and providing support for deep learning workflows.

Design and implement high-speed SerDes (80Gbps+) from transistor-level architecture through layout, verification, and silicon characterization. Optimize circuits for noise, power, and loop stability in FinFET/deep-submicron CMOS nodes. Collaborate with layout on floorplanning and high-speed routing. Lead post-silicon bring-up, debugging, modeling, and top-level verification of analog and digital blocks.

Design and build real-time, physics-informed AI models and synthetic data pipelines for quantum calibration and decoding. Develop surrogate models and GPU-accelerated implementations, apply reinforcement and online learning for calibration policies, co-design low-latency calibration-decoding systems, and collaborate across engineering and research to enable fault-tolerant quantum hardware.

Design, build, and operate HTOL/burn-in boards and ovens per JEDEC. Perform thermal management, test-script/vector debugging, data analysis (Python/MATLAB), vendor collaboration, and reliability database improvements to ensure silicon reliability.