Top Tech Jobs & Startup Jobs

Lead architecture and delivery of next-generation system-level power management and optimization across silicon, platform, software, manufacturing, and product systems. Define power feature requirements, develop power modeling/measurement methodologies, correlate silicon behavior with simulations, and drive productization from architecture to silicon. Collaborate cross-functionally and with offshore teams to improve performance for datacenter and client devices.

Lead the System Integration team to ensure timely delivery of silicon programs, enhancing test capabilities, resolving complex system issues, and mentoring talent.

Lead design and delivery of SMAC workflow methodology and infrastructure to keep system specifications and manufacturing test specs aligned. Build production-grade Python pipelines, automated checks, CI gates, and agent-ready tooling that detect spec drift pre-silicon. Integrate workflows into program milestones, drive cross-org adoption across design, operations, and DFX, and apply AI where appropriate while ensuring reviewable, auditable artifacts.

Architect and deliver voltage-noise mitigation across silicon, package, board, and platform. Define product noise targets, build Sim-to-Si correlation, model and prototype transient/noise features, lead bringup bug resolution, and drive cross-functional co-design tradeoffs to ship robust PDN solutions.

Technical lead accountable for end-to-end chip integrity on a major silicon program. Guide feature integration, resolve multi-functional post-silicon bugs (HBM, power, I/O, packaging), steward qualification playbooks, surface risks and decision-ready options for executives, mentor other chip leads, and run critical debug and technical execution forums.

The role involves owning physics models, defining manufacturing specifications, and validating designs to ensure product quality and performance. The architect will utilize first-principles thinking and AI to improve workflows and drive alignment across engineering teams.

Lead rebuilding NVIDIA's silicon productization toolchain using applied AI: simulate power and binning, convert silicon behavior into context-engineered AI agents, integrate tools into an agent harness, drive eval-driven development and CI gates, and mentor engineers to deploy LLM-backed production services that protect product quality.

Lead the Test, Manufacturability, Reliability & Quality organization for GPU, SoC, and CPU programs. Ensure technical execution, resolve multi-functional failures, and develop a high-performing engineering team.

Lead post-silicon memory bring-up, characterization, and qualification for GDDR/LPDDR/HBM on GPU/CPU/SoC. Root-cause ambiguous multi-domain memory failures, productize fixes and playbooks, and build AI-enabled workflows to analyze shmoo/margin data and accelerate qualification across global teams.

The role involves architecting and integrating power and performance management features, leading debugging efforts, and collaborating across teams to optimize product efficiency in silicon development.