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The DFP Engineer designs manufacturing test methodologies, translating product requirements into tests, ensuring quality, yield, and throughput for silicon products.

The Senior Silicon and System Product Lead at NVIDIA will innovate and drive next-generation silicon and system products, overseeing market analysis, performance optimization, and cross-functional collaboration throughout development.

Lead silicon speed characterization from first power-on to production sign-off. Close correlation gaps between pre-silicon models and measured silicon, trace frequency/timing failures to root causes, drive fixes across teams, and build AI-driven test orchestration and analysis pipelines to expand coverage and reduce cycle time.

Lead the planning and execution of chip bringup, coordinating multi-functional teams, improving methodologies, and driving process improvements for silicon development.

Lead design and optimization of next-generation high-speed IOs (NVLink, NVLink-C2C), focusing on IO power management, power/performance modeling, interoperability, and deep debug across cross-functional teams to enable product bringup and release.

Work with architects, hardware, firmware, and test teams to co-design and verify system-level speed and reliability features. Develop verification collateral, automation and AI/LLM-assisted tooling, perform pre- and post-silicon characterization and tester-to-system correlation, and lead debug of complex silicon issues to ensure on-time product shipment.

Lead Product Co-Design and Verification at NVIDIA, focusing on Speed, Reliability, and Power Compliance. Oversee system design and verification, mentor engineers, and collaborate with various teams to achieve high-quality product outcomes.

Lead architecture and delivery of an ML infrastructure efficiency platform across silicon co-design teams. Define platform contracts, onboarding, orchestration, auth, observability, storage/caching, and SLA enforcement. Own production operation, security, reliability, and performance while mentoring engineers and driving cross-team technical decisions.

Lead HBM and LPDDR system integration and bringup for next-generation SoCs. Own memory performance, power, thermal, and reliability closure across silicon, package, board, and firmware. Drive post-silicon margining, VF shmoo, eye characterization, and correlation. Debug training, calibration, SI/PI, and system stability issues. Define validation, characterization, and issue-tracking plans to produce production-ready operating points.

Lead architecture and delivery of next-generation system-level power management and optimization across silicon, platform, software, manufacturing, and product systems. Define power feature requirements, develop power modeling/measurement methodologies, correlate silicon behavior with simulations, and drive productization from architecture to silicon. Collaborate cross-functionally and with offshore teams to improve performance for datacenter and client devices.