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Design, build, extend, test, deploy, and maintain a centralized CI/CD infrastructure for open-source accelerated computing projects. Collaborate across teams, define CI/CD best practices, debug production issues, support other teams, and mentor junior engineers while setting technical direction and standards.

Design, build, extend, test, deploy, and maintain a centralized CI/CD infrastructure for open-source accelerated computing projects. Collaborate with teams, support platform users, ensure reliability/security/compliance, and debug production issues across the stack.

Design and deploy rack-scale AI infrastructure and cluster solutions for NVIDIA products. Collaborate with product teams and cross-functional engineering groups to onboard hardware/software stacks, optimize cluster deployments, and support multi-site datacenter and lab rollouts. Troubleshoot complex system failures, automate provisioning, and improve time-to-market for next-generation GPU/Tegra-based products.

Develop algorithms and optimizations for inference and compiler stack, enhance performance metrics, collaborate with hardware teams, and publish work on novel approaches.

Own and implement DFT architectures and test access mechanisms (IEEE standards, memory BIST, scan, memory dump, DFX security); architect and deploy DFT methodologies across RTL, verification, and pattern generation; collaborate with timing, physical design, software, bringup and production teams; perform silicon debug and ATE bring-up; mentor junior engineers on test design trade-offs.

Lead design and deployment of advanced silicon test methodologies, own cross-functional implementation of scan, BIST, and scan compression, and drive chip bring-up from pre-silicon to production. Develop standardized bring-up processes, mentor junior engineers, collaborate with VLSI and product teams, and validate test patterns and debug silicon failures.

Develop and improve NVIDIA GPU compiler back end: investigate issues, implement code generation improvements, and collaborate with global compiler, hardware, and application teams to emit high-performance GPU machine instructions for graphics and compute workloads.

The Senior Mask Layout Design Engineer will perform physical layout for mixed-signal designs, collaborate with engineers, and ensure compliance with design rules.

Drive physical design for CPUs, GPUs, and SoCs, focusing on netlist aspects, timing convergence, and utilizing EDA tools for high-frequency, low-power designs.

The role involves developing device drivers for network interface cards, optimizing software solutions, and addressing complex technical issues in the Linux kernel group.