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The role involves collaborating on AI GPU deployment, optimizing performance, mentoring engineers, and improving user experience on NVIDIA RTX platforms.

As a Senior Deep Learning Systems Engineer, you will optimize datacenters for AI applications by analyzing performance metrics and developing software tools.

Develop and integrate full-system functional models for CPU architectures, support CPU architects, and enhance system software for performance modeling.

The role involves developing automated tests and tools for NVIDIA software, focusing on improving quality and efficiency through Python programming and AI-assisted development tools.

Lead failure analysis and product verification for NVIDIA's chips, collaborate with cross-functional teams, and develop AI-driven workflows to enhance yield and quality.

Define high-level SoC subsystem and I/O architecture for LPU products, translate product requirements into architecture and IP specifications, build and validate functional/architectural models (C++, SystemC, Python), and drive tradeoffs across performance, power, reliability, and security while coordinating with IP, firmware, software, RTL, verification, and post-silicon teams.

Lead DRAM memory firmware from architecture through production: design and implement initialization and training sequences, characterize and tune interfaces across PVT corners, drive bring-up and validation, root-cause hardware/software issues, set firmware quality standards, and mentor junior engineers.

Design, develop, test, and optimize system software for next-generation ARM SoCs in pre- and post-silicon phases. Analyze system-wide performance bottlenecks, recommend HW/SW policies, perform competitive workload comparisons, and drive full-stack adoption of performance optimizations across NVIDIA software and OSS SDKs.

Drive physical design for CPUs, GPUs, and SoCs focusing on netlist-related tasks, logic synthesis, and timing closure. Help in ECO generation.

Design and architect multi-GPU systems for AI and HPC, focusing on high-speed interconnects and hardware-software co-design, while collaborating with various engineering teams.