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Design and simulate photonic integrated circuit building blocks and optical interfaces; derive PIC specifications; perform IC floorplanning and layout; characterize high-speed optical link electrical and optical blocks; develop test equipment and support production testing and qualification for space- and ground-deployed PICs.

Lead IC layout discipline for RF and analog blocks: floorplanning, power/ground distribution, pad placement, custom RF/analog layout, DRC/ERC/LVS checks, top-level integration, foundry tape-out, EDA tool evaluation, and mentoring/guides for layout techniques.

Lead IC layout discipline for custom RF and analog blocks: floorplanning, power/ground distribution, pad placement, block layout with attention to matching and parasitics, verification (DRC/ERC/LVS), top-level integration, GDS generation and manufacturability checks, tool trials, and documentation.

Design, simulate, and characterize electro-optical and RF/analog/mixed-signal circuits and photonics building blocks for silicon photonics PIC/EIC. Perform floorplanning, layout, packaging and parasitic modeling, collaborate with cross-functional teams, develop test equipment and production qualification processes for high-speed optical links supporting space and ground deployments.

Design, simulate, and analyze photonic integrated circuit building blocks and package optical interfaces. Specify PIC systems, perform IC floorplanning/layout, characterize high-speed electrical and optical components, develop automated test equipment, and support production testing in collaboration with cross-disciplinary teams.

Design, simulate, and characterize RF/analog/mixed-signal ICs for space and ground systems. Derive specs, perform floorplanning and layout, model package parasitics, validate prototypes, analyze radio performance, and support test automation and production qualification.

Lead IC layout work for RF and mixed-signal chips, defining floorplans, power/ground distribution and pad placement. Perform block and top-level layout, DRC/ERC/LVS checks, tape-out steps, and collaborate with packaging, EDA vendors, and cross-disciplinary teams. Mentor peers by generating layout guides and drive manufacturability and foundry handoff for advanced-node silicon targeting high-frequency RF blocks.

Design, simulate and model RF/analog/mixed-signal ICs in SiGe or CMOS; derive RFIC specifications; perform floorplanning, layout, and parasitic/package modeling; evaluate and characterize prototypes and full radio performance; develop automated test lab equipment; and work with systems, modem/DSP, ASIC, and manufacturing teams for production testing and qualification.

Design, simulate, and characterize RF/analog/mixed-signal ICs for space and ground deployments. Derive RFIC specifications, perform floorplanning and layout, model package parasitics, validate prototypes, analyze radio performance, and support production testing and automated lab equipment development with cross-disciplinary teams.

Design, test, and qualify RF/microwave circuits, MMICs, RFICs, modules and SiP solutions across cellular to mmWave bands. Develop test hardware and procedures, derive RF system/block specifications, and support production test and debug with manufacturing and customer teams.