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Lead digital ASIC verification at block and system level: write and execute test plans, develop test harnesses and regressions, close coverage, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex digital designs.

Lead digital ASIC verification at block and system levels: author and execute test plans, develop test harnesses and regressions, drive coverage closure, support pre-silicon verification, chip bring-up and post-silicon validation, and collaborate with cross-disciplinary teams to verify complex designs.

Design and implement RF and analog IC layouts for advanced-node silicon, collaborate on floorplanning, power/ground distribution and packaging, run DRC/ERC/LVS and manufacturability checks, integrate top-level layout and ESD/pad assemblies, and support EDA tool trials and team training.

Lead a team to ensure Starlink hardware reliability from factory to field: define strategy, run root-cause investigations, develop reliability qualification and testing, automate test/data analysis, drive production quality and process improvements, monitor field metrics, and mentor engineers while ensuring ISO/quality compliance.

Develop and execute digital ASIC verification at block and system levels. Create SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon, chip bring-up and post-silicon validation.

Support and improve EDA/IC design environments for RFIC and silicon teams: triage tool/PDK/HPC issues, maintain wrappers and runbooks, build lightweight automation and QA tests, manage PDK deployments, and partner with design, foundry, IT, and vendors to improve reproducibility and methodology.

Develop and execute digital ASIC verification at block and system levels. Build SystemVerilog/UVM and non-UVM testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification, chip bring-up, and post-silicon validation.

Verify digital ASICs at block and system level: write and execute test plans, build SystemVerilog (UVM and non-UVM) testbenches, run regressions and close coverage, automate tests with Python/MATLAB, and support pre-silicon verification, chip bring-up and post-silicon validation.

Develop and execute digital ASIC verification at block and system level. Build SystemVerilog (UVM and non-UVM) testbenches, write test plans, run regressions, close coverage, automate test generation with Python and MATLAB, and support pre-silicon verification through post-silicon validation and chip bring-up.

Support and improve EDA/CAD workflows for RFIC and silicon teams by triaging tool/PDK issues, maintaining tool wrappers and runbooks, building lightweight automation and QA tests, partnering with vendors and foundries, and converting recurring support items into durable flow improvements.