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Lead and participate in complex ASIC physical implementations across synthesis, DFT, floorplanning, P&R, clock and power methodology, timing closure, signal integrity, and physical verification using multiple EDA tool flows.

The Verification Engineer will develop verification plans, maintain UVM-based testbenches, analyze simulations, and collaborate with teams to ensure design quality.

Design, develop, and execute validation and verification tests for mainframe applications. Build and maintain test automation pipelines in CI/CD, assess coverage, automate tasks via scripting, and collaborate within Agile teams to ensure high-quality software delivery.

Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.

Design and co-develop automated production test systems for silicon photonics products. Create hardware configurations, test scripts, data acquisition modules, and GUIs; support product characterization, validation, yield improvement, and process control.

Translate schematics into DRC/LVS-clean layouts for critical analog/RF IP blocks, collaborate on floorplanning, power/ground architecture, and device matching, and carry designs from initial floorplan through tape-out using industry EDA tools on advanced FinFET nodes.

Senior individual-contributor software engineer responsible for designing, developing, and maintaining NetMaster and SOLVE product features on z/OS. Work includes parsing SMF/zERT records, debugging production mainframe issues, writing tests, leading design/code reviews, mentoring junior engineers, and collaborating with product owners and architects to deliver robust, maintainable software.

The Hardware Engineer will evaluate silicon technology for IP and product designs, focusing on technology assessment, design enablement, and collaboration with foundry and design teams. Responsibilities include test structure layout, simulation, silicon characterization, and ensuring design quality across multiple projects.

Lead DFT planning and integration using Siemens Tessent. Manage ATPG/ATE interfaces, ATE bring-up and failure analysis. Drive test-time reduction, implement DFT across multi-power domains, and perform synthesis, formal verification, STA and simulation for DFT modes while troubleshooting and improving DFT flows.

Lead import compliance for customs and import operations, ensuring adherence to CBP regulations, HTS classification, valuation, country of origin, duty preference programs, and CTPAT. Manage brokers, documentation, audits, policy development, cross-functional coordination with engineering/logistics/procurement, and training to scale import compliance programs and maintain audit-ready records.