Top Tech Jobs & Startup Jobs

2 Months AgoSaved
In-Office
Fort Collins, CO, USA
91K-146K Annually
Senior level
91K-146K Annually
Senior level
Software • Semiconductor • Manufacturing
Develop and sustain dry etch processes for silicon-based MEMS technologies in R&D and high-volume manufacturing. Responsibilities include evaluating materials and applications, optimizing and controlling processes, conducting DOE and data analysis, resolving yield and defect issues, documenting improvements, transferring processes into production, and collaborating with engineering, operations, and equipment maintenance teams.
Top Skills: Design Of Experiments (Doe)Dry EtchMemsSemiconductor ManufacturingStatistical Process Control
Reposted 2 Months AgoSaved
In-Office
San Jose, CA, USA
144K-230K Annually
Senior level
144K-230K Annually
Senior level
Software • Semiconductor • Manufacturing
Lead and manage customer ASIC programs from RFQ through production. Advise on EDA flows, perform physical design and STA checks, assess risks, coordinate cross-functional mitigation, and support tape-out quality. Engage with customers and internal teams on IP, packaging, test, and production, and mentor teams on best practices.
Top Skills: Design For Test (Dft)DrcEda ToolsLogic SimulationLogic SynthesisMemory BistPhysical DesignSerdesShellStatic Timing Analysis (Sta)TclVerilog
Reposted 2 Months AgoSaved
In-Office
2 Locations
108K-173K Annually
Senior level
108K-173K Annually
Senior level
Software • Semiconductor • Manufacturing
Lead architecture and design of high-performance clocking solutions. Manage full lifecycle of analog timing IPs and validation, ensuring integration into SoCs.
Top Skills: ArcsimMatlab
Reposted 2 Months AgoSaved
In-Office
2 Locations
101K-162K Annually
Mid level
101K-162K Annually
Mid level
Software • Semiconductor • Manufacturing
Design and execute block- and chip-level verification for high-speed interconnect ASICs. Build SystemVerilog UVM testbenches, validate IEEE Ethernet protocols, understand chip architecture, and create scripts/tools to improve verification efficiency. Collaborate with architecture, firmware, physical and layout teams throughout product development.
Top Skills: AsicCC++HdlIeee EthernetPerlPythonSystemverilogSystemverilog UvmTclVerilogVhdl
Reposted 2 Months AgoSaved
In-Office
2 Locations
122K-195K Annually
Senior level
122K-195K Annually
Senior level
Software • Semiconductor • Manufacturing
Develop and optimize ATE test programs and test hardware for high-speed networking switches. Debug failures, reduce test time, perform volume data analysis, collaborate with design and production teams, and support extreme temperature ASIC testing.
Top Skills: AtePcb DesignProbe/Socket HardwareSerdes (>100G)Teradyne Ultraflex
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Reposted 2 Months AgoSaved
In-Office
2 Locations
110K-176K Annually
Senior level
110K-176K Annually
Senior level
Software • Semiconductor • Manufacturing
Translate schematics into DRC/LVS-clean layouts for critical analog/RF IP blocks, collaborate on floorplanning, power/ground architecture, and device matching, and carry designs from initial floorplan through tape-out using industry EDA tools on advanced FinFET nodes.
Top Skills: Cadence VirtuosoDrcFinfetLvsMentor CalibrePllSerdesVirtuoso Vxl
Reposted 2 Months AgoSaved
In-Office
Irvine, CA, USA
108K-173K Annually
Senior level
108K-173K Annually
Senior level
Software • Semiconductor • Manufacturing
The Hardware Engineer will evaluate silicon technology for IP and product designs, focusing on technology assessment, design enablement, and collaboration with foundry and design teams. Responsibilities include test structure layout, simulation, silicon characterization, and ensuring design quality across multiple projects.
Top Skills: Cmos TechnologyEda ToolsRcx ToolsSpice Simulation
Reposted 2 Months AgoSaved
In-Office
Warrenville, IL, USA
110K-176K Annually
Senior level
110K-176K Annually
Senior level
Software • Semiconductor • Manufacturing
Design, develop, and execute validation and verification tests for mainframe applications. Build and maintain test automation pipelines in CI/CD, assess coverage, automate tasks via scripting, and collaborate within Agile teams to ensure high-quality software delivery.
Top Skills: Ci/CdEsm (Enterprise Security Management)JenkinsJob Control Language (Jcl)JSONMainframePythonRexx
Reposted 2 Months AgoSaved
In-Office
2 Locations
52-83 Hourly
Senior level
52-83 Hourly
Senior level
Software • Semiconductor • Manufacturing
Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.
Top Skills: Cadence ConformalCadence Rtl CompilerGitPerlPrimetimeSpyglass LintSvnSynopsys Design CompilerSynopsys FormalityTclVerilog
2 Months AgoSaved
In-Office
San Jose, CA, USA
122K-195K Annually
Senior level
122K-195K Annually
Senior level
Software • Semiconductor • Manufacturing
Develops and deploys semiconductor timing sign-off flows using Python, Perl, Tcl, and Unix shell. Responsibilities include EDA flow development for PrimeTime, Tempus, Innovus, and RedHawk; automation; statistical data analysis and modeling; and support for chip design teams. The role requires advanced digital IC design expertise, strong communication, multitasking, problem-solving, and collaboration across projects.
Top Skills: Continuous DeliveryContinuous IntegrationInnovusIssue ManagementPerlPrimetimePythonRedhawkRevision ControlTclTempusUnix Shell
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