Top Tech Jobs & Startup Jobs

Lead full physical IC design flow from RTL to tape-out including synthesis, place-and-route, clock tree synthesis, timing closure, EM/IR analysis, floorplanning, and physical verification. Develop flows and methodologies, collaborate with RTL designers, and perform EDA tool scripting and automation. On-site role at San Jose.

The Supply Chain Planning Analyst will support planning efforts, manage ERP issues, forecast production, and drive improvements in manufacturing processes at Broadcom.

Design, develop, test, and debug mainframe applications using Assembler (HLASM) and related mainframe technologies. Collaborate in Agile teams, mentor junior engineers, automate tasks with scripting, drive engineering excellence, and modernize enterprise mainframe software.

Develop, test, and support mainframe database software within an Agile team. Participate in design/code reviews, sprint activities, customer interactions, and drive quality, security, and efficiency improvements.

Senior Digital VLSI Design Engineer responsible for defining and enforcing multi-clock synchronization, creating synthesis constraints, and driving full-chip CDC/RDC and DFT sign-off. Collaborate with architecture and chip leads to identify metastability and reset issues pre-RTL freeze, mentor teams, and implement automated sign-off flows for complex high-speed IPs.

Lead advanced packaging R&D for multi-chip AI/HPC modules. Define technology roadmaps, drive assembly process development and qualification, perform failure analysis and yield/parametric data analysis, run thermal/stress simulation, manage projects through transfer to high-volume manufacturing, and coordinate with foundries, OSATs, and internal design/validation teams.

Integrate and maintain commercial AI tools and LLM agents into VLSI design flows, coordinate multi-agent systems, optimize performance and QoR, deploy AI agents and chatbots, preprocess data, evaluate solutions, and train end-users to improve design productivity.

Design and deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below). Perform PPA optimization, CDC/RDC analysis, low-power design, timing closure, and hand off to physical design. Collaborate with Architecture, Verification, and Physical Design teams and drive SoC integration for high-speed memory and SerDes protocols.

Act as the Product Owner for AI-powered mainframe application understanding and impact analysis: maintain and prioritize backlog, refine stories, coordinate cross-functional teams, engage customers for feedback, and represent the customer voice to R&D and leadership to maximize product value.

Design and execute verification plans for IP blocks and systems using SystemVerilog/UVM. Build testbenches, develop Python behavioral models, analyze simulations, debug failures, maintain automation/regression frameworks, and collaborate with design and architecture teams to improve verification methodologies and resolve root causes.