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Lead cross-functional teams to plan, execute, and deliver analog/mixed-signal IP (high-speed serial IO and die-to-die interfaces) from concept through post-silicon validation and launch. Track program status with data, drive technical problem resolution, ensure schedule and quality, communicate to stakeholders, and continuously improve execution practices while developing team capabilities.

Lead end-to-end verification for chassis and interconnect IPs, build scalable UVM/SystemVerilog testbenches, drive simulation/formal convergence and coverage closure, collaborate with architecture/design/software, mentor engineers, and ensure functional signoff and performance/power goals.

Lead design, integration, and verification of analog/mixed-signal IP for high-speed IO and die-to-die interfaces. Develop circuits (PLLs, ADCs, RX/TX, regulators), floorplans, bump maps, and power delivery; perform transistor-level design, simulation, post-silicon validation, and signal integrity analysis while mentoring junior engineers and collaborating across global teams.

Define and own adapter/IPU/DPU/NIC card and platform architectures, driving integration across SoC, board, firmware, OEMs and data center requirements. Specify manageability, thermal/power, reliability, and serviceability; lead cross-functional reviews and deliver actionable architecture artifacts and roadmaps.

Lead design and development of integrated AI systems combining hardware, software, firmware, board, and silicon. Define system architectures, optimize performance, implement and benchmark solutions, and translate business opportunities into product specifications. Innovate in reinforcement learning, vision, simulation, and robotics while mentoring technical leaders and influencing Intel's AI product roadmap.

Drive performance verification and circuit quality signoff for CPU designs, evaluate new process nodes, and manage pre-to-post silicon correlation and debugging. Requires experience in circuit design and STA.

Lead and manage a 10–15 person analog design team to deliver high-speed analog/mixed-signal IP from concept through silicon. Provide technical leadership in analog circuit design and validation, drive project schedules and efficiency, collaborate cross-functionally, and develop engineers while supporting on-site lab bring-up and post-silicon validation.

Lead supplier quality and manufacturing-availability improvements for a semiconductor factory: manage supplier issues (8D, MQI), drive root-cause analysis and cost savings, define KPIs, collaborate with cross-functional teams, and mentor junior SCEs to improve yield, reliability, and performance.

The NPI Integrator will lead new product/process introduction, coordinating documentation, tracking processes, and ensuring product compliance through development cycles.

The Physical Design Timing Engineer will perform SOC level timing analysis, ensuring designs meet performance and functionality requirements, collaborating with various teams to optimize solutions.