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The Senior AI SoC Design Engineer will define microarchitecture, implement RTL designs, ensure design quality, and collaborate across teams to develop advanced AI hardware solutions.

Develop electro-optical architectures and optimize integrated electro-photonic components for next-generation optical interconnects. Lead cross-functional R&D, create simulation methodologies and mixed-signal/digital accelerators, advise post-silicon test plans, and document designs for scalable electro-photonic systems.

Lead data governance and operations to drive business transformation. Define and execute data governance strategy, improve master data for ERP and supply chain, and oversee data quality, security, and privacy. Serve as liaison between business and IT, manage budget and team development, and report progress to senior leadership.

Develop and optimize assembly processes, equipment, and material specifications for semiconductor package manufacturing. Use DOE/SPC and reliability testing to improve yield, quality, cost, and manufacturability; collaborate with suppliers and cross-functional teams to qualify products and resolve packaging issues.

Design, develop, test, and debug software tools, flows, and methodologies for design automation. Capture user requirements, write functional and test code, automate builds/deployments, and perform unit, integration, and end-to-end testing of EDA tools and related workflows.

Lead end-to-end architecture of SoC compute complexes and high-performance memory subsystems for IPU/DPU platforms. Define CPU cluster designs, cache hierarchies, coherency models, DDR/HBM memory controllers, SMMU/IOMMU virtualization, and system-level integration with networking, storage, and accelerators. Optimize performance, power, scalability, and multi-generation roadmaps while collaborating across firmware, drivers, validation, and performance teams.

Design, develop, validate, and deploy mathematical models, optimization algorithms, and simulation tools to solve semiconductor manufacturing and supply chain problems. Collaborate with business units to define requirements, identify root causes, and implement solutions for factory performance, production scheduling, equipment optimization, and distribution network operations.

Lead end-to-end network subsystem architecture for next-generation IPU/DPU SoCs, defining packet pipelines, protocol engines, QoS/scheduling, telemetry, and scalability. Drive cross-functional architecture decisions, customer engagements, and multi-generation roadmap for hyperscale data center networking.

Lead architecture strategy for multi-die chiplet SoC platforms: define chiplet partitioning, D2D interconnect and QoS, power/clock/boot infrastructure, RAS/debug/telemetry, and system-level PPA/cost/yield trade studies. Drive cross-functional alignment and produce executive architecture recommendations for scalable data-center networking SoCs.

Lead development and optimization of thin film deposition processes (CVD, ALD, PVD, epitaxy, thermal/plasma) to improve yield, uniformity, throughput, and cost. Drive defect reduction, equipment optimization, cross-functional problem resolution, and supplier collaboration to transition technologies from development to high-volume manufacturing for advanced Intel nodes.