Top Tech Jobs & Startup Jobs

Design, develop, and optimize oneCCL communication library features for low-latency, high-throughput HPC workloads. Collaborate with scientists and hardware teams on Aurora supercomputer integrations, implement and enhance communication protocols, benchmark and analyze performance across configurations, and debug complex cross-layer hardware/software issues.

Design and optimize advanced embedded memory IP (SRAM, register files, ROM) for Intel CMOS processes. Perform memory pathfinding, PPA optimization, custom circuit design, layout and automation, pre-silicon verification and post-silicon validation/debug to enable yield and product ramp. Collaborate with domain experts, EDA vendors, and product teams to deliver memory collaterals and test chips.

The role involves analyzing user information, documenting business processes, training users, supporting testing, and managing data configurations with Windchill PLM.

The CPU Physical Design Engineer will implement custom CPU designs, conduct physical design flow, optimize designs, and collaborate on verification processes. They will work with EDA vendors and enhance methodologies for CPU design.

Design and optimize semiconductor packaging processes and equipment; apply DOE/SPC and statistical methods; design test equipment for environmental and mechanical stress; ensure manufacturability and material specifications; collaborate with suppliers; lead problem-solving and continuous improvement; standardize qualification and quality systems.

Develop and prototype software and modeling solutions for factory automation. Perform discrete event simulation, statistical analysis, and modeling to solve manufacturing and stochastic systems problems. Collaborate with cross-functional teams and industry partners to validate ideas and drive manufacturing roadmap improvements.

Lead architecture of RDMA transports and datacenter fabrics for large-scale AI, cloud, and HPC. Define transport protocols, congestion and flow control, reliability, and collective communication optimizations across silicon, firmware, and software to improve cluster performance and scalability.

Lead physical design for neuromorphic silicon: architect floorplans, define timing/power constraints, run synthesis/place-and-route, debug timing/EM/IR/LVS/DRC, run back-annotated simulations, script and automate EDA flows, and drive block- and chip-level closure to meet power, performance, and area targets.

Design and implement CPU RTL for integer, floating point, and reservation station logic. Drive RTL coding, simulation, and optimization for power, performance, area, and timing. Participate in architecture definition, review verification plans, resolve RTL test failures, and provide technical leadership and cross-team collaboration to deliver CPU IP for full-chip integration.

Lead front-end RTL methodology for CPU design, leveraging AI tools to improve RTL coding, debug, and logic optimization. Drive methodology and architectural discussions, collaborate with architecture and backend teams, and deliver CPU IP meeting power, performance, area, and timing goals. Provide technical leadership and build a high-performing team.