Top Tech Jobs & Startup Jobs

Reposted 2 Months AgoSaved
In-Office
Mountain View, CA, USA
196K-257K Annually
Senior level
196K-257K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
As a Design Verification Engineer, collaborate with digital, analog, and photonic designers to ensure robust design verification through methodologies, test plans, and performance validation.
Top Skills: ModelsimPythonQuestaSystemverilogUvmVcsXcelium
Reposted 2 Months AgoSaved
In-Office
Mountain View, CA, USA
187K-220K Annually
Senior level
187K-220K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Develop and execute high-speed serial I/O characterization and validation across platforms. Architect test concepts and DFT rules, operate lab equipment, automate measurements with Python, define stress tests, troubleshoot compliance and DUT issues, and collaborate cross-functionally to transition designs to high-volume manufacturing.
Top Skills: AwgBertCdrCtleDfeFecFfeIeee 802.3ObrOifOscilloscopeOvaPciePllPnaPolarization SynthesizerPower MeterPpgPythonSerdesSilicon PhotonicsSpectrum AnalyzerTdrTransceiverTunable LaserUsb4Vna
Reposted 2 Months AgoSaved
In-Office
2 Locations
175K-220K Annually
Senior level
175K-220K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Develop and extend device software and firmware for photonic processors and interconnects. Define control plane, diagnostics, and monitoring; integrate with datacenter administration (CMIS, OpenBMC, DMTF). Implement security, telemetry, virtualization, and remote administration. Debug embedded systems, collaborate across hardware and software teams, and participate in customer engagements to gather requirements.
Top Skills: C++CmakeCmisDevice DriversDmtfEmbedded SystemsGdbGitJtagKernel DevelopmentLinuxLogic AnalyzersOpenbmcOptical CommunicationPhotonic TransceiversPython
2 Months AgoSaved
In-Office
Mountain View, CA, USA
169K-244K Annually
Senior level
169K-244K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Lead thermo-mechanical simulation and validation for advanced photonics packaging. Develop FEA models (stress, warpage, solder collapse), run multi-physics analyses, identify failure modes, drive material/process solutions, and scale simulation with Python/MATLAB automation. Collaborate with vendors and cross-functional teams to prototype, characterize, and document methodologies that ensure assembly, optical alignment, thermal, and reliability requirements are met.
Top Skills: 3D PackagingAbaqusAnsysBgaFinite Element AnalysisFlip-ChipMatlabPythonSolder Joint Fatigue ModelingThermal-Structural CouplingWafer-Level PackagingWarpage Analysis
Reposted 2 Months AgoSaved
In-Office
2 Locations
146K-222K Annually
Mid level
146K-222K Annually
Mid level
Artificial Intelligence • Hardware • Machine Learning • Software
Define and specify system-level digital architectures for high-speed mixed-signal photonic communication chips. Collaborate with digital, analog, photonic, firmware, and test teams to enable SerDes, ADC/DAC, modulators, and receivers from concept through production. Produce and validate architectural specifications and work with RTL and verification teams to ensure implementation and test alignment.
Top Skills: AdcCad ToolsDacDvIbis-AmiMatlabPhotonic DetectorsPhotonic ModulatorsPythonRtlSerdesSpice
New

Track Smarter, Apply Better.

Ditch the spreadsheets. Organize your job search with our freeApplication Tracker.

Use For Free
Application Tracker Preview
Reposted 2 Months AgoSaved
In-Office
2 Locations
149K-217K Annually
Expert/Leader
149K-217K Annually
Expert/Leader
Artificial Intelligence • Hardware • Machine Learning • Software
Design and architect high-speed (50G+) analog/mixed-signal circuit blocks for optical transceivers, collaborate with analog, digital, photonics, and software teams to model and analyze solutions, produce and validate architectural specifications, and represent technical leadership externally.
Top Skills: AdcAdvanced CmosCadence SpectreCadence VirtuosoCdrsCtleDacDfeDriversIbis-AmiMach-Zehnder ModulatorsMicroring ModulatorsOptical TransceiversPllsSilicon PhotonicsTiasVerilog-A
Reposted 2 Months AgoSaved
In-Office
Mountain View, CA, USA
217K-256K Annually
Expert/Leader
217K-256K Annually
Expert/Leader
Artificial Intelligence • Hardware • Machine Learning • Software
Lead hardware systems development for silicon-photonics AI accelerators and interconnects, owning PCB/board/system design through production, integration, verification, and cross-functional coordination while mentoring engineers and maintaining documentation and test/validation processes.
Top Skills: Advanced PackagingEthernetHigh-Density Pcb DesignHigh-Speed SerdesI2CI3CJtagOptical TransceiversPcbaPcieQspiSilicon PhotonicsSpiVrms
Reposted 2 Months AgoSaved
In-Office
Mountain View, CA, USA
300K-350K Annually
Expert/Leader
300K-350K Annually
Expert/Leader
Artificial Intelligence • Hardware • Machine Learning • Software
The Principal Machine Learning Infrastructure Researcher will design and model performance for ML systems using Lightmatter technology while leading a small team and publishing research findings.
Top Skills: Ai SystemsDeep LearningEthernetGpusInfinibandLarge Language ModelsMachine LearningNvlinkTpus
2 Months AgoSaved
In-Office
2 Locations
175K-230K Annually
Expert/Leader
175K-230K Annually
Expert/Leader
Artificial Intelligence • Hardware • Machine Learning • Software
Design and layout block- and chip-scale silicon photonic circuits from concept through tapeout and bring-up. Collaborate with analog, digital, packaging, product, and architecture teams to floorplan and integrate on-chip photonics, perform layout-driven simulation and verification, troubleshoot performance bottlenecks, improve layout/verification flows and PDKs, and support photonic product development and publications.
Top Skills: Cadence VirtuosoGdsfactoryGdsiiPdkPythonSilicon Photonics
Reposted 2 Months AgoSaved
In-Office
Boston, MA, USA
217K-267K Annually
Senior level
217K-267K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Lead STA sign-off and timing closure for silicon-photonics ASICs across process nodes. Develop timing constraints, run full-chip STA, automate ECOs with Tempus/PrimeTime, collaborate with RTL/DFT/architecture teams, and document best practices for synthesis through PnR and tapeout signoff.
Top Skills: Asic StaCadenceCmosDftPerlPlace And Route (Pnr)PrimetimePythonRtlShellSilicon PhotonicsSynopsysTclTempusTiming Constraints
All Filters
JobType
New Jobs
Job Category
Experience
Industry
Company Name
Company Size

Sign up now Access later

Create Free Account