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The Principal Machine Learning Infrastructure Researcher will design and model performance for ML systems using Lightmatter technology while leading a small team and publishing research findings.

Lead development of end-to-end 3D package assembly, test, and fiber-attach processes. Define test chip requirements, develop assembly/test design rules, plan DOEs, analyze reliability risks, and collaborate with foundries, OSATs, and internal architects to ensure manufacturability, performance, and high yields. Document and present results to stakeholders.

Design and develop power, control, mixed-signal, and high‑speed interconnect circuits; perform board bring-up, verification, and troubleshooting; run test plans to validate board and system performance; collaborate cross‑functionally from concept through production and maintain design documentation.

Design, execute, and analyze reliability tests for photonics and semiconductor products. Develop test plans, perform FMEA and root-cause analysis, model reliability statistically, and drive cross-functional improvements to meet durability and compliance targets.

Design and layout block- and chip-scale silicon photonic circuits from concept through tapeout and bring-up. Collaborate with analog, digital, packaging, product, and architecture teams to floorplan and integrate on-chip photonics, perform layout-driven simulation and verification, troubleshoot performance bottlenecks, improve layout/verification flows and PDKs, and support photonic product development and publications.

Lead STA sign-off and timing closure for silicon-photonics ASICs across process nodes. Develop timing constraints, run full-chip STA, automate ECOs with Tempus/PrimeTime, collaborate with RTL/DFT/architecture teams, and document best practices for synthesis through PnR and tapeout signoff.

Develop and maintain photonics PDK components and pcells, ensure synchronization between layouts, netlists, and models, author LVS/DRC decks, perform device extraction and LVS troubleshooting, build automated regression and CI pipelines, and collaborate across design, layout, and modeling teams to support tape-outs.