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Reposted 2 Days AgoSaved
In-Office
2 Locations
230K-270K Annually
Expert/Leader
230K-270K Annually
Expert/Leader
Artificial Intelligence • Hardware • Machine Learning • Software
Lead design of high-speed analog/mixed-signal transceivers for silicon photonics systems. Drive block specifications with cross-functional teams, run post-layout and mixed-signal simulations, validate circuits in lab, define test plans, document designs, and mentor junior engineers.
Top Skills: 3D Em Simulation ToolsCmosFinfetMatlabMzmPythonRing ModulatorsSerdesSilicon PhotonicsSystemverilogTrans-Impedance Amplifier (Tia)Tx DriverVerilogams
Reposted 2 Days AgoSaved
In-Office
2 Locations
245K-321K Annually
Expert/Leader
245K-321K Annually
Expert/Leader
Artificial Intelligence • Hardware • Machine Learning • Software
Lead development of end-to-end 2D/3D and wafer-scale package assembly, test, and fiber-attach processes. Define test-chip requirements, run design-of-experiments, address reliability and thermal/mechanical issues, and coordinate with foundries, OSATs, and architects to ensure manufacturable, high-yield designs.
Top Skills: 2D Packaging3D PackagingDesign Of ExperimentsFiber Attach MethodsMechanical ModelingPhotonics PackagingTest Chip DesignThermal ModelingWafer-Scale Packaging
3 Days AgoSaved
In-Office
3 Locations
135K-212K Annually
Senior level
135K-212K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
The Staff Mechanical Engineer will focus on mechanical design, structural analysis, GD&T, and FEA to enhance packaging technologies for AI architectures at Lightmatter.
Top Skills: AbaqusAnsysAutocadFinite Element Analysis (Fea)Geometric Dimensioning And Tolerancing (Gd&T)Mechanical EngineeringSolidworks
3 Days AgoSaved
In-Office
Mountain View, CA, USA
220K-270K Annually
Senior level
220K-270K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
The Physical Design Timing Engineer will drive backend digital execution, focusing on timing constraints, analysis, and closure on advanced CMOS technologies. Responsibilities include STA sign-off, collaborating with multiple teams, managing timing complexities, and automating timing ECO generation.
Top Skills: CadencePerlPythonShellSynopsysTcl
Reposted 3 Days AgoSaved
In-Office
Mountain View, CA, USA
224K-257K Annually
Senior level
224K-257K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
As a Design Verification Engineer, collaborate with digital, analog, and photonic designers to ensure robust design verification through methodologies, test plans, and performance validation.
Top Skills: ModelsimPythonQuestaSystemverilogUvmVcsXcelium
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Reposted 3 Days AgoSaved
In-Office
2 Locations
170K-230K Annually
Senior level
170K-230K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Design, layout, and test photonic devices while collaborating with various teams to integrate and validate products in high-volume manufacturing.
Top Skills: Ansys FdtdPhoton DesignPythonSilicon PhotonicsTidy3D
Reposted 3 Days AgoSaved
In-Office
2 Locations
190K-230K Annually
Senior level
190K-230K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Design analog and mixed-signal circuits for optical communication systems, collaborate with architects, and validate circuit performance in the lab.
Top Skills: AmplifiersAnalog CircuitsCadence Design EnvironmentData ConvertersMixed-Signal Circuits
Reposted 4 Days AgoSaved
In-Office
Mountain View, CA, USA
43-47 Annually
Internship
43-47 Annually
Internship
Artificial Intelligence • Hardware • Machine Learning • Software
As a Reliability Test Intern, you will conduct reliability tests, set up testing environments, and analyze data to present to stakeholders.
Top Skills: MultimetersOscilloscopesPythonTest Automation ToolsThermal Sensors
5 Days AgoSaved
In-Office
Mountain View, CA, USA
195K-214K Annually
Senior level
195K-214K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
The Staff Physical Design Engineer will implement digital blocks using advanced tech nodes, focusing on timing closure and power integrity, while collaborating with teams on ASIC design.
Top Skills: Cadence ToolsPythonShellTcl
Reposted 5 Days AgoSaved
In-Office
Mountain View, CA, USA
195K-214K Annually
Senior level
195K-214K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Develop microarchitecture design and RTL for ML/AI accelerator ASICs while collaborating with various engineering teams to ensure high performance and low power designs.
Top Skills: Asic DesignCommunication ProtocolsHigh-Speed Digital DesignMemory SystemsPower-Efficient Digital DesignRtl
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