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The role involves developing firmware for photonic products, collaborating across teams, defining architectures, and integrating with Data Center capabilities.

Lead hands-on verification and characterization of high-speed electro-optic links: run lab measurements, build channel models, verify link budgets, characterize BER/eye/jitter/equalization, support silicon bring-up and cross-team debug, influence architecture, mentor engineers, and build automation tools.

Lead transition of next-gen hardware from design to mass production. Oversee product lifecycle, supplier readiness, ramp management, schedule, and financial targets.

Lead STA sign-off and timing closure for silicon-photonics ASICs across process nodes. Develop timing constraints, run full-chip STA, automate ECOs with Tempus/PrimeTime, collaborate with RTL/DFT/architecture teams, and document best practices for synthesis through PnR and tapeout signoff.

Develop and maintain photonics PDK components and pcells, ensure synchronization between layouts, netlists, and models, author LVS/DRC decks, perform device extraction and LVS troubleshooting, build automated regression and CI pipelines, and collaborate across design, layout, and modeling teams to support tape-outs.

Lead development of the internal photonics PDK: create Python-based pcells, build and verify compact models for active/passive devices, automate parameter extraction from FDTD/FEM solvers, validate models against lab measurements, implement CI/regression testing, and own netlist extraction and connectivity logic to ensure accurate system-level simulation.

Lead development of the internal photonics PDK and component library. Build Python-based pcells, create and validate compact models for active and passive devices, automate parameter extraction from electromagnetic solvers, and correlate models with lab measurements. Implement regression testing, CI pipelines, and robust netlist/connectivity logic to ensure layout, models, and simulations remain synchronized.

The Staff Mechanical Engineer will focus on mechanical design, structural analysis, GD&T, and FEA to enhance packaging technologies for AI architectures at Lightmatter.

The Physical Design Timing Engineer will drive backend digital execution, focusing on timing constraints, analysis, and closure on advanced CMOS technologies. Responsibilities include STA sign-off, collaborating with multiple teams, managing timing complexities, and automating timing ECO generation.

The Staff Physical Design Engineer will implement digital blocks using advanced tech nodes, focusing on timing closure and power integrity, while collaborating with teams on ASIC design.