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2 Months AgoSaved
In-Office
Mountain View, CA, USA
157K-176K Annually
Mid level
157K-176K Annually
Mid level
Artificial Intelligence • Hardware • Machine Learning • Software
Design and analyze power delivery networks for high-performance compute SoCs across package and system architectures. Perform electromagnetic, time-domain, and frequency-domain simulations; model regulators; evaluate voltage droop and overshoot; conduct lab measurements; and collaborate with hardware, layout, and systems teams to improve power integrity. Document analyses, support design reviews, monitor layout constraints, and contribute to architectural tradeoff studies.
Top Skills: 2.5D Packaging2D Packaging3D PackagingDc-Dc ConvertersH-SpiceIdemKeysight AdsMatlabN-Port ModelsNetwork AnalyzersOscilloscopesPcb DesignPowerdcPowersiProgrammable LoadsPythonSkillTcl
2 Months AgoSaved
In-Office
Mountain View, CA, USA
157K-176K Annually
Senior level
157K-176K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Drive signal integrity engineering for high-speed photonics and computing products from architecture through lab validation. Analyze PCIe, UCIe, and SerDes channels using S-parameters, eye and jitter analysis, equalization, and simulation tools. Collaborate with hardware and PCB layout teams on impedance, routing, termination, and packaging. Perform measurements with oscilloscopes, VNAs, network analyzers, and TDRs, troubleshoot issues, support design reviews, and document results and guidelines.
Top Skills: Ansys HfssAnsys SiwaveI2CJavaScriptKeysight AdsNetwork AnalyzersOcean ScriptsOscilloscopesPciePythonSerdesSkillSpiTdrsUcieVnas
2 Months AgoSaved
In-Office
Mountain View, CA, USA
157K-176K Annually
Senior level
157K-176K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Designs IC package substrate layouts for standard and advanced packaging technologies. Responsibilities include package floorplanning, stack-up optimization, signal and power integrity routing, DFM/DFA closure, fab-file generation, supplier and OSAT coordination, package tape-outs, and design automation. The role supports analog, digital, and photonics package architectures, including multi-chiplet and 2.5D/3D packaging solutions.
Top Skills: 2.5D/3D Ic PackagingAllegro X ApdAltiumCadence Integrity 3DicDie-To-Die InterfacesEmibExpedition Package DesignerFan-Out Chip-On-WaferHybrid BondingIc Package SubstratesMicro-BumpsOrganic MaterialsPads LayoutPythonSilicon InterposersSkill
Reposted 2 Months AgoSaved
In-Office
Mountain View, CA, USA
220K-270K Annually
Senior level
220K-270K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
The Staff Physical Design Engineer will implement digital blocks using advanced tech nodes, focusing on timing closure and power integrity, while collaborating with teams on ASIC design.
Top Skills: Cadence ToolsPythonShellTcl
Reposted 2 Months AgoSaved
In-Office
Boston, MA, USA
217K-267K Annually
Senior level
217K-267K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Implement and sign off complex digital blocks from synthesis through physical verification in advanced process nodes. Drive full-chip STA and timing closure, power analysis, floorplanning, IO and clock distribution, DRC/LVS cleanup, and functional/timing ECOs. Automate flows with TCL/Python/Shell, collaborate across teams, and work with EDA vendors to resolve tool issues.
Top Skills: 3Nm Process NodeAsic Physical DesignCadenceDrcEm/Ir Signoff ToolsLvsPythonShellSilicon Photonics LayoutSta (Static Timing Analysis)Tcl
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Reposted 2 Months AgoSaved
In-Office
2 Locations
230K-267K Annually
Expert/Leader
230K-267K Annually
Expert/Leader
Artificial Intelligence • Hardware • Machine Learning • Software
The Photonics Technical Lead will create scalable laser solutions for silicon photonics AI communications, collaborating across teams to ensure design feasibility and meet performance specifications.
Top Skills: Control SystemsHardware EngineeringPhotonic DevicesPhotonic Integrated CircuitsSemiconductor PhysicsSilicon Photonics
Reposted 2 Months AgoSaved
In-Office
Boston, MA, USA
206K-236K Annually
Senior level
206K-236K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Lead design verification for integrated digital, analog, and photonic devices using UVM, mixed-signal/AMS methods, RNM, and emulation. Define DV methodology, create reusable testbenches, run block and full-chip verification, integrate analog IP and behavioral models, close coverage and signoff, and collaborate with architects and designers for performance and post-silicon validation.
Top Skills: AmsBehavioral ModelingEmulationFormal VerificationMixed-Signal SimulationModelsimPerformance ModelingPost-Silicon ValidationPythonQuestaReal Number Modeling (Rnm)SystemverilogUvmVcsXcelium
Reposted 2 Months AgoSaved
In-Office
2 Locations
217K-325K Annually
Expert/Leader
217K-325K Annually
Expert/Leader
Artificial Intelligence • Hardware • Machine Learning • Software
The Sr./Principal Mixed-Signal Digital Architect will design digital circuits for photonic-based communication, collaborate with teams, and lead product development.
Top Skills: Cad ToolsChip DesignDigital Design FlowFirmwareHigh-Speed Ams ElectronicsIbis-Ami SimulatorsMatlabPythonSoftwareSpice Simulators
Reposted 2 Months AgoSaved
In-Office
Mountain View, CA, USA
187K-260K Annually
Senior level
187K-260K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
The engineer will architect wafer, package, and system level characterization and test strategies for silicon photonics products, and work closely with architecture and design teams, vendors, and validation teams.
Top Skills: AwgDcaDsoLcaPnaPythonSilicon Photonics
Reposted 2 Months AgoSaved
In-Office
Mountain View, CA, USA
165K-245K Annually
Senior level
165K-245K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Software
Develop high-speed analog transceiver solutions while collaborating with architects and engineers for optical communication systems.
Top Skills: 3D Electro-Magnetic Simulation ToolsCadence Design Environment
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