Leads development of next-generation AI accelerator chips from architecture and RTL through tapeout, silicon bring-up, qualification, and production. Oversees hardware engineering teams, ASIC program execution, technical tradeoffs, design reviews, external semiconductor partners, and hardware/software co-design. Collaborates with architecture, software, systems, product, and executive teams while managing risks, milestones, manufacturing considerations, and organizational growth.

Define and drive system-level architectures for next-generation AI and edge-computing SoCs. Responsibilities include specifying memory, interconnect, coherency, I/O, security, and power architectures; evaluating performance, power, area, cost, and schedule tradeoffs; modeling AI workloads; guiding cross-functional RTL, verification, firmware, compiler, and application teams; and supporting validation, silicon bring-up, characterization, and optimization.

Own product positioning, messaging, pricing strategy, go-to-market plans, launches, competitive intelligence, sales enablement, and market-development programs for AI accelerator hardware and software. Translate technical capabilities into customer value, guide market requirements, enable sales and partners, develop proof points, and measure adoption, pipeline influence, and design-win opportunities across edge and data-center markets.