Top Tech Jobs & Startup Jobs

Reposted 2 Months AgoSaved
Remote
US
159K-196K Annually
Senior level
159K-196K Annually
Senior level
Automotive
Lead procurement strategy for engineering services and R&D hardware, manage high-volume outsourced engineering contracts, negotiate complex commercial and IP terms, structure SOWs/NREs/JDM/ODM agreements, optimize manufacturing relationships, perform make-vs-buy analyses, partner with Legal on IP and cybersecurity, and present TCO to Finance and Hardware leadership to support rapid hardware prototyping and development.
Top Skills: Ariba P2PE-SourcingSpend Analysis Tools
Reposted 2 Months AgoSaved
In-Office
3 Locations
213K-263K Annually
Senior level
213K-263K Annually
Senior level
Automotive
The Senior Software Engineer will drive the architecture of core services for evaluation workflows, mentor junior engineers, and ensure APIs meet evaluation complexities.
Top Skills: C++Python
Reposted 2 Months AgoSaved
In-Office
2 Locations
213K-263K Annually
Senior level
213K-263K Annually
Senior level
Automotive
Build and productionize large-scale data pipelines and platforms to generate ML and evaluation datasets from driving logs and simulation data. Design tools for data mining, exploration, and analysis, and collaborate with Data Science and Quantitative Analytics to deliver high-impact, production-ready infrastructure and dataset generation.
Top Skills: A/B Experiment InfrastructureC++Distributed SystemsPythonSQL
Reposted 2 Months AgoSaved
In-Office
2 Locations
152K-187K Annually
Senior level
152K-187K Annually
Senior level
Automotive
Manage EHS programs, ensure compliance with regulations, lead incident investigations, and provide EHS leadership for operations across multiple sites.
Top Skills: Ehs Software PlatformsEnvironmental Management SystemsEpaIso 14001Iso 45001Osha
Reposted 2 Months AgoSaved
In-Office
Mountain View, CA, USA
175K-215K Annually
Mid level
175K-215K Annually
Mid level
Automotive
Design and execute comprehensive verification plans for custom silicon, developing UVM/SystemVerilog testbenches, reference models, and stimulus. Build scalable automation in Python, integrate VIP, define coverage metrics, debug RTL/testbench/software interactions, and drive verification best practices across teams.
Top Skills: C++Constrained-Random GenerationDdr5EthernetFormal VerificationFunctional CoverageGenerative Ai/LlmsHbmNoc (Network-On-Chip)Pcie Gen5Pcie Gen6PythonRtlSva (Systemverilog Assertions)SystemverilogTestbench DevelopmentUpf (Power-Aware Verification)UvmVerification Ip (Vip)
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