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Lead design and implementation of digital IC/ASIC/SoC for medical imaging technology, owning RTL and validation processes with collaboration across teams.

Lead end-to-end program management for silicon development and embedded integrations. Oversee execution from architecture to commercialization, managing cross-functional teams and partner relations.

Lead end-to-end program management for silicon development and partner-facing integrations, ensuring execution meets technical, regulatory, and commercialization milestones.

The Regional Vice President II leads revenue growth and enterprise sales for Butterfly Network, focusing on hospitals and health systems. Key responsibilities include full sales cycle management, strategic territory planning, and establishing executive relationships, driving adoption of medical imaging technology across assigned regional accounts.

As a Senior QA Engineer, you'll ensure high-quality software delivery through design and execution of test cases across various platforms, lead validations, and collaborate with teams for defect management and quality improvements.

As a BDR in the Vet Team, you will identify and qualify veterinary customers, generate leads, assist in building team processes, and close business, contributing to Butterfly Network's growth in the animal health market.

Design and implement digital ASICs, develop low-power RTL, integrate multiple embedded processors, and collaborate on functional verification and post-silicon debug.

As a Staff Engineer in Digital ASIC Design, you will lead digital IC design projects, ensuring successful tapeout cycles and collaboration with verification teams for functional closure.

The Regional Vice President II leads sales growth and adoption of Butterfly Network's products in hospitals, focusing on enterprise sales and consultative strategies. Responsibilities include managing relationships, driving sales cycles, and collaborating with cross-functional teams while ensuring customer satisfaction and meeting sales quotas.

The Principal Engineer, Physical Design Verification is responsible for leading physical verification signoff processes for digital SoCs and ensuring successful tapeouts, utilizing advanced methodologies and tools.