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As a Materials Planning Engineer, you will manage forecasts for spares and materials, improve manufacturing efficiencies, and collaborate across teams to ensure optimal material availability and budgeting compliance.

The role involves defining advanced package architectures, conducting trade-off studies, building models, running simulations, and providing architectural direction for memory systems.

The Principal Node Development Product Engineer drives product readiness by collaborating with various teams, analyzing silicon data, and addressing integration risks in DRAM technology development.

The Thin Films Engineer develops deposition processes for EUV-enabled DRAM, focusing on process optimization and defect reduction while collaborating with multifunctional teams.

Design block-level layouts using Cadence Virtuoso including floorplanning, placement, routing, and optimization. Apply physical constraints (PDN, pin placement, routing blockages), ensure DRC/LVS/density/reliability compliance, support parasitic extraction, post-layout verification, ECOs, and create partial custom layouts for device-level or small analog blocks while collaborating with cross-site teams.

The Photolithography Process Engineer supports lithography operations, monitors tool health, executes control plans and assists in process improvements.

The HVAC/R Operations Technician will maintain and operate HVAC systems, perform routine maintenance, respond to system failures, and ensure compliance with safety standards.

Lead a global Process Hazard Analysis organization to deliver risk-based process safety for new tools, chemistries, and facilities. Drive hazard assessments, incident investigations, root-cause analysis, corrective actions, and transferable safety standards while partnering across engineering, EHS, manufacturing, facilities, and suppliers.

Lead design, optimization, verification, and modeling of high-speed IO and clocking circuits for DRAM products. Develop simulation and analysis methodologies, support silicon correlation with product engineering and SI teams, and collaborate with process and transistor modeling groups to push circuit speed limits and meet timing budgets.

Design, optimize, and verify analog and mixed-signal blocks for DRAM. Leverage AI and EDA flows for circuit optimization, improve verification and yield, support post-layout simulation and silicon correlation, mentor junior designers, and independently define technical solutions.