Top Tech Jobs & Startup Jobs

The US Expansion Planning Engineer at Micron will optimize equipment capacity, analyze financial data related to new equipment, and improve planning processes through collaboration and data analysis.

Design and implement SystemVerilog RTL and microarchitectures for AI-optimized memory systems; perform synthesis and PPA analysis; document microarchitecture; evaluate tradeoffs and drive implementations from specification through silicon.

Hands-on PhD internship developing and optimizing 3D DRAM photolithography processes. Collaborate with cross-functional teams to perform experiments, root-cause analyses, statistical analysis, and apply data-driven and AI methods. Present project results to technical and leadership teams.

Lead product ownership for ID1 smart manufacturing solutions: gather fab requirements, define user stories and acceptance criteria, manage backlog, drive UAT and deployments, partner with engineering and data teams to deliver AI/ML-enabled dashboards and integrations, and ensure shop-floor adoption to improve wafer movement, cycle time, equipment uptime and output.

Design and analyze digital and analog memory circuits (arrays, control logic, datapaths, decoders) using simulation and layout tools. Optimize power, speed, die size, manufacturability, and apply AI-enabled tools to improve design flow while collaborating with cross-functional teams for validation and product readiness.

The Frontend Central Process Integration Senior Engineer leads process optimization across global semiconductor operations, improves yield, and resolves manufacturing issues by collaborating with cross-functional teams.

Design, layout, simulate, and optimize DRAM memory circuits focusing on performance, power, area, and manufacturability. Develop schematics for arrays, control logic, decoders, datapaths, and test circuitry, validate designs via SPICE/Verilog simulations, integrate parasitics, and support test chip development and silicon validation with AI-enabled improvements.

Lead development and scale-up of bonding processes for 3D memory products, focusing on chip-to-wafer and hybrid bonding, while driving technical direction and collaborating with multiple teams.

Lead global efforts to improve pump, abatement, and chiller (PAC) system performance, reliability, and cost efficiency across semiconductor sites. Drive continuous improvement, standardize processes and Best Known Methods, manage projects from planning through implementation, analyze performance data with sites and suppliers, and communicate progress while promoting safety, sustainability, and knowledge sharing.

Lead SSD hardware development across the product lifecycle: architecture, high-speed SI/PI analysis, PCB/schematic design, lab validation and debugging, manufacturing readiness, cross-functional integration, and mentorship. Apply AI-enabled tools to accelerate validation, automation, and debugging workflows.