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Lead RTL micro-architecture and implementation for advanced ASICs from concept to silicon. Develop and debug complex RTL, integrate IP, support front-end flows (lint/CDC/synthesis/ECO), collaborate with verification/STA/physical teams, and build automation and AI-assisted tools to improve productivity and quality.

Lead PCB design from requirements through release for complex, high-speed boards. Perform pre-layout planning (stackup, constraints, placement), create manufacturable layouts in Cadence Allegro, coordinate cross-functionally, develop design rules and standards, support fabrication/assembly, and drive continuous improvement.

Develop and optimize EUV mask blank materials and processes for High-NA EUV readiness. Translate lithography requirements into manufacturable mask solutions, run DOE-driven R&D, collaborate with OPC, design, lithography, and FEOL teams, and transition technologies to production.

The Principal SoC DFT Engineer will lead DFT architecture and implementation for complex HBM SoC designs, collaborating with various teams to ensure manufacturable test solutions throughout the product lifecycle.

Lead development and optimization of plasma dry etch processes for advanced DRAM and 3D device structures. Design experiments, perform root-cause analysis, analyze data to improve yield and capability, collaborate with integration, manufacturing, equipment, and vendor teams, and support process transfer to production.

Lead commercial ownership of construction and professional services suppliers for capital projects: negotiate contracts, manage supplier performance, apply quantity surveying and cost management, advise project teams on procurement and risk, drive cost reduction and supplier strategy, and coordinate cross-functional stakeholders to ensure contract compliance and financial controls.

Design and implement digital ASIC logic across the full ASIC lifecycle: specifications, microarchitecture, RTL (SystemVerilog), simulation, synthesis, static timing analysis, timing closure, linting, CDC, and top-level integration. Leverage GenAI and agentic tools, collaborate cross-functionally, and support interfaces such as PCIe, NVMe, DRAM, NAND, and AXI.

Lead electrical characterization of advanced DRAM and emerging memory devices, driving methodology development and collaborating with cross-functional teams to connect device behavior to reliability and performance.

The HBM SOC Design Engineer is responsible for designing and developing HBM DRAM products, collaborating with multi-functional teams to enhance performance and quality. Key tasks include RTL development, IP integration, and addressing technical challenges in designs.

Support development of advanced process technology through CAD, scripting, and automation tools for product development and physical design.