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Lead RTL design for DRAM digital and mixed-signal IP from specification through silicon signoff. Architect and implement high-performance, power- and area-efficient RTL, perform front-end quality checks (lint, CDC/RDC, synthesis, UPF, STA), collaborate with physical design and verification teams to meet PPA/timing goals, and improve RTL methodologies and automation.

As a Staff Verification Architect, you'll design verification plans and solutions for HBM products, mentor engineers, and drive methodology improvements to enhance quality and efficiency in verification processes.

As a Memory Design Engineer specializing in HBM, you will develop and validate memory, logic, and analog circuits, collaborating with cross-functional teams to ensure product success.

The Staff Cloud Solutions Architect will lead technology strategy for cloud and enterprise accounts, build customer relationships, guide solution design, and influence product roadmaps.

Own and grow a strategic global Hyperscale customer relationship: create and execute account plans, build senior-level relationships, manage multi-product pipeline and forecasts, meet revenue and margin targets, identify strategic opportunities, and align cross-functional teams to deliver Micron solutions and market intelligence.

Lead startup, development, and optimization of diffusion processes for DRAM manufacturing. Improve yield, reduce cost, resolve production issues, manage SPC charts, and collaborate with equipment, integration, and cross-functional teams to drive productivity and quality improvements.

The Principal HBM Design Architect will design, simulate, and optimize DRAM circuits for high-bandwidth memory products, collaborating across teams to ensure functionality and performance.

Design, simulate, analyze, and optimize CMOS memory circuits and functional blocks for DRAM and emerging memory technologies. Support physical design, run circuit simulations and debugging with industry tools, collaborate cross-functionally, and use AI-assisted and automation tools to improve design productivity and tape-out readiness.

Lead CMOS device innovation and develop next-generation DRAM and Compute-in-Memory solutions. Drive device and module development and collaborate with multi-disciplinary teams to optimize performance metrics.

Design, simulate, and optimize digital and analog DRAM circuits for high-bandwidth memory products while collaborating with global teams and ensuring functional accuracy across designs.