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The Principal SoC DFT Engineer will lead DFT architecture and implementation for complex HBM SoC designs, collaborating with various teams to ensure manufacturable test solutions throughout the product lifecycle.

Design and deploy EDA/CAD software, automation, and AI-assisted tools to accelerate custom IC and memory design workflows. Collaborate with global design and CAD teams to integrate LLMs, AI agents, and EDA tool flows for layout, verification, simulation, and tape-out automation.

Define end-to-end ESD and latch-up architecture for next-generation HBM across base die, DRAM stacks, TSVs, and advanced packaging. Develop protection strategies, standards, rule decks, and signoff criteria; correlate design assumptions with silicon validation and field reliability; and partner with foundry and packaging teams to solve system-level ESD challenges.

Develop firmware verification plans and test methodologies for enterprise SSDs and NVMe features. Build Python-based automation, reporting, and data-collection tools; analyze regression failures and perform root-cause analysis. Apply machine learning, AI-powered tools, and data-driven methods to improve test efficiency, failure detection, and workflow automation. Collaborate with firmware engineers, test developers, and AI/ML practitioners to improve product quality and reliability.

Manage the CMP process engineering team supporting new product introduction, facility qualification, manufacturing ramp, yield, and quality performance at Micron’s Boise fab. Responsibilities include hiring and developing engineers, ensuring safety compliance, partnering with suppliers, transferring products from technology development to manufacturing, establishing supplier accountability, and coordinating global manufacturing alignment.

Leads semiconductor PVD/CVD area manufacturing performance by resolving systemic issues, improving throughput and cycle time, managing capacity planning, assessing operational risks, and guiding capital decisions. Partners with manufacturing, process development, industrial engineering, and operations teams to execute improvement projects and capacity strategies. Analyzes operational data, leads strategic meetings, and drives safety, quality, audit, and procedural consistency initiatives.

Develop and optimize wet cleaning and resist strip processes for EUV and DUV photomasks. Design experiments, analyze defect, contamination, yield, and equipment data, characterize process equipment, evaluate tool matching, and support qualification and corrective actions. Apply statistical analysis, data science, and machine learning to identify process trends and improve yield. Lead an independent project and present technical recommendations to engineering teams and leadership.

Develop comprehensive DRAM system architectures, lead optimization across hardware layers, and interact with customers to translate requirements into silicon designs.

The role involves leading initiatives for process improvement and collaboration across multiple teams to enhance yield performance in product integration engineering.

As a Process Integration Engineer, you will develop and integrate new technology for DRAM memory, optimize performance, and collaborate across teams to enhance production processes.