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The position involves supporting BEOL process flow development for DRAM technologies, troubleshooting integration issues, analyzing data for yield improvement, collaborating with teams, and learning statistical tools.

Lead sourcing and evaluation of Seed to Series B venture investments, drive company-wide AI/ML initiatives, manage portfolio relationships, prepare executive briefings, and mentor team members while partnering cross-functionally to align investments with Micron's strategy.

Lead development, installation, qualification, and optimization of photolithography track equipment and recipes. Investigate process excursions, fix defects and uniformity issues, coordinate suppliers and cross-functional teams, and drive solutions to improve yield, cost, and throughput for high-volume semiconductor manufacturing.

The DRAM Architect will optimize DRAM solutions by developing system/component solutions, collaborating with teams, and analyzing system behavior to enhance performance and efficiency.

The HBM SOC Design Engineer is responsible for designing and developing HBM DRAM products, collaborating with multi-functional teams to enhance performance and quality. Key tasks include RTL development, IP integration, and addressing technical challenges in designs.

The Principal SoC DFT Engineer will lead DFT architecture and implementation for complex HBM SoC designs, collaborating with various teams to ensure manufacturable test solutions throughout the product lifecycle.

Design and deploy EDA/CAD software, automation, and AI-assisted tools to accelerate custom IC and memory design workflows. Collaborate with global design and CAD teams to integrate LLMs, AI agents, and EDA tool flows for layout, verification, simulation, and tape-out automation.

Define end-to-end ESD and latch-up architecture for next-generation HBM across base die, DRAM stacks, TSVs, and advanced packaging. Develop protection strategies, standards, rule decks, and signoff criteria; correlate design assumptions with silicon validation and field reliability; and partner with foundry and packaging teams to solve system-level ESD challenges.

Develop firmware verification plans and test methodologies for enterprise SSDs and NVMe features. Build Python-based automation, reporting, and data-collection tools; analyze regression failures and perform root-cause analysis. Apply machine learning, AI-powered tools, and data-driven methods to improve test efficiency, failure detection, and workflow automation. Collaborate with firmware engineers, test developers, and AI/ML practitioners to improve product quality and reliability.

Manage the CMP process engineering team supporting new product introduction, facility qualification, manufacturing ramp, yield, and quality performance at Micron’s Boise fab. Responsibilities include hiring and developing engineers, ensuring safety compliance, partnering with suppliers, transferring products from technology development to manufacturing, establishing supplier accountability, and coordinating global manufacturing alignment.