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Work with engineers and scientists to develop and optimize CMP processes and chemistries for future semiconductor nodes using experimentation, characterization, data analysis, and AI-enabled tools. Prepare technical reports and present findings to R&D teams while supporting process capability, productivity, contamination control, and surface/interface characterization improvements.

The role involves architecting and optimizing high-speed datapath circuitry for HBM products, defining system requirements, coordinatiing designs, and addressing support challenges across teams. It requires extensive collaboration for effective integration and performance enhancement.

Design, build, and maintain scalable full-stack applications with cloud-native microservices and REST APIs. Integrate AI capabilities (LLMs, RAG, agentic workflows), ensure performance, observability, and reliability, own the full SDLC, and partner with stakeholders to deliver resilient, production-grade solutions.

Analyze DRAM power behavior, develop and maintain power models and tools, perform workload-based and IDD characterization, define power targets, and partner with design and architecture teams to drive power-performance tradeoffs across product development.

Lead NAND Flash memory architecture and design efforts from concept to production. Drive feature evaluation, simulation planning, verification, parasitic extraction debugging, and post-silicon validation. Coordinate cross-functional teams (marketing, test, process, product engineering), mentor on CAD/modeling/verification, and push methodology and AI tool adoption to optimize die size, performance, reliability, and power.

As a Design Verification Engineer at Micron, you'll lead innovation in DRAM design and verification, mentor engineers, and drive improvements in methodologies.

Lead end-to-end DRAM circuit design and optimization across memory array, control logic, datapath, and test logic. Perform SPICE and Verilog simulations, incorporate layout parasitics, evaluate power/performance/area trade-offs, define validation/test-chip strategies, and collaborate with cross-functional teams to enable manufacturable, high-performance DRAM products.

Design and produce multi-dimensional semiconductor layouts from schematics, lead major block developments, verify data integrity, improve layout efficiency via automation, collaborate across global design and CAD teams, and deliver quality-controlled layouts on schedule.

Lead layout-driven architecture exploration for next-generation memory modules and form factors. Evaluate form factor, routing topology, and pinout tradeoffs; define routing and manufacturing feasibility, SI/PI budgets, and layout constraints for >10-20+ Gb/s signaling. Drive adoption of advanced PCB technologies, collaborate with SI/PI teams, influence industry standards, perform risk/tradeoff analysis, and mentor junior engineers.

Lead daily laboratory and site operations for the San Jose Global Engineering Labs site, partnering with engineering, facilities, EHS, and business teams. Manage space utilization, equipment lifecycle, infrastructure planning, budgets, projects, and continuous improvement initiatives. Build customer relationships, drive safety and operational excellence, coach and develop staff, and use data and AI-enabled tools to improve decision making and service delivery.