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Lead LPDDR-based module architecture and system-level optimization for AI inference at the edge. Analyze system architectures with modeling, simulation, and prototypes, identify bottlenecks with customers, define DRAM features to boost AI performance, lead pathfinding, and mentor junior engineers.

Design and conduct experiments for signal and power integrity characterization, provide EMI/EMC guidance, and enhance measurement methodologies.

The Principal HBM Design Architect will design, analyze, and optimize DRAM circuits, collaborating with multi-functional teams to develop high-performance HBM technologies.

Coordinate product supply and inventory to meet revenue and customer commitments using analytics, optimization, and planning systems. Troubleshoot supply-demand mismatches with Tableau, SQL, Excel macros, and SPO tools. Apply supply chain science—constraint-based planning, safety stock, mix optimization, and scenario modeling—while collaborating across manufacturing, sales, engineering, and logistics to publish supply responses and guide manufacturing and replenishment strategies.

Work with engineers and scientists to develop and optimize CMP processes and chemistries for future semiconductor nodes using experimentation, characterization, data analysis, and AI-enabled tools. Prepare technical reports and present findings to R&D teams while supporting process capability, productivity, contamination control, and surface/interface characterization improvements.

The role involves architecting and optimizing high-speed datapath circuitry for HBM products, defining system requirements, coordinatiing designs, and addressing support challenges across teams. It requires extensive collaboration for effective integration and performance enhancement.

Design, build, and maintain scalable full-stack applications with cloud-native microservices and REST APIs. Integrate AI capabilities (LLMs, RAG, agentic workflows), ensure performance, observability, and reliability, own the full SDLC, and partner with stakeholders to deliver resilient, production-grade solutions.

Analyze DRAM power behavior, develop and maintain power models and tools, perform workload-based and IDD characterization, define power targets, and partner with design and architecture teams to drive power-performance tradeoffs across product development.

Lead NAND Flash memory architecture and design efforts from concept to production. Drive feature evaluation, simulation planning, verification, parasitic extraction debugging, and post-silicon validation. Coordinate cross-functional teams (marketing, test, process, product engineering), mentor on CAD/modeling/verification, and push methodology and AI tool adoption to optimize die size, performance, reliability, and power.

As a Design Verification Engineer at Micron, you'll lead innovation in DRAM design and verification, mentor engineers, and drive improvements in methodologies.